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3d579c11e0
Add the clock binding doc for i.MXRT1170. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2022
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* Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMXRT1170_H
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#define __DT_BINDINGS_CLOCK_IMXRT1170_H
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#define IMXRT1170_CLK_DUMMY 0
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#define IMXRT1170_CLK_OSC 1
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#define IMXRT1170_CLK_OSC_32K 2
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#define IMXRT1170_CLK_RCOSC_16M 3
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#define IMXRT1170_CLK_RCOSC_48M 4
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#define IMXRT1170_CLK_RCOSC_48M_DIV2 5
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#define IMXRT1170_CLK_RCOSC_400M 6
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#define IMXRT1170_CLK_PLL_ARM 7
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#define IMXRT1170_CLK_PLL_AUDIO 8
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#define IMXRT1170_CLK_PLL_VIDEO 9
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#define IMXRT1170_CLK_PLL1 10
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#define IMXRT1170_CLK_PLL1_DIV2 11
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#define IMXRT1170_CLK_PLL1_DIV5 12
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#define IMXRT1170_CLK_PLL2 13
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#define IMXRT1170_CLK_PLL2_PFD0 14
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#define IMXRT1170_CLK_PLL2_PFD1 15
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#define IMXRT1170_CLK_PLL2_PFD2 16
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#define IMXRT1170_CLK_PLL2_PFD3 17
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#define IMXRT1170_CLK_PLL3 18
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#define IMXRT1170_CLK_PLL3_DIV2 19
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#define IMXRT1170_CLK_PLL3_PFD0 20
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#define IMXRT1170_CLK_PLL3_PFD1 21
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#define IMXRT1170_CLK_PLL3_PFD2 22
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#define IMXRT1170_CLK_PLL3_PFD3 23
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#define IMXRT1170_CLK_M7 24
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#define IMXRT1170_CLK_M4 25
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#define IMXRT1170_CLK_BUS 26
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#define IMXRT1170_CLK_BUS_LPSR 27
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#define IMXRT1170_CLK_LPUART1_SEL 28
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#define IMXRT1170_CLK_LPUART1 29
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#define IMXRT1170_CLK_USDHC1_SEL 30
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#define IMXRT1170_CLK_USDHC1 31
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#define IMXRT1170_CLK_GPT1_SEL 32
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#define IMXRT1170_CLK_GPT1 33
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#define IMXRT1170_CLK_SEMC_SEL 34
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#define IMXRT1170_CLK_SEMC 35
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#define IMXRT1170_CLK_END 36
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#endif /* __DT_BINDINGS_CLOCK_IMXRT1170_H */
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