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Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. The ICID macros for SEC needed to be adapted because the format of the registers is different. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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| .. | ||
| ddr.c | ||
| ddr.h | ||
| eth_ls1088aqds.c | ||
| eth_ls1088ardb.c | ||
| Kconfig | ||
| ls1088a_qixis.h | ||
| ls1088a.c | ||
| MAINTAINERS | ||
| Makefile | ||
| README | ||
Overview
--------
The LS1088A Reference Design (RDB) is a high-performance computing,
evaluation, and development platform that supports ARM SoC LS1088A and its
derivatives.
LS1088A SoC Overview
--------------------------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
RDB Default Switch Settings (1: ON; 0: OFF)
-------------------------------------------
For QSPI Boot
SW1 0011 0001
SW2 x100 0000
SW3 1111 0010
SW4 1001 0011
SW5 1111 0000
For SD Boot
SW1 0010 0000
SW2 0100 0000
SW3 1111 0010
SW4 1001 0011
SW5 1111 0000
For eMMC Boot
SW1 0010 0000
SW2 1100 0000
SW3 1111 0010
SW4 1001 0011
SW5 1111 0000
Alternately you can use this command to switch from QSPI to SD
=> i2c mw 66 0x60 0x20; i2c mw 66 10 10;i2c mw 66 10 21
LS1088ARDB board Overview
-------------------------
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- XFI
- QSGMII
- DDR Controller
- One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
with FSL refernce software is 2100MT/s
- 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
- IFC/Local Bus
- One 2 GB NAND flash with ECC support, not as boot source
- CPLD of size 2K
- USB 3.0
- Two high speed USB 3.0 ports
- First USB 3.0 port configured as Host with Type-A connector
- Second USB 3.0 port configured as OTG with micro-AB connector
- SDHC/eMMC
- SDHC slot and onboard eMMC are muxed together
- 4 I2C controllers
- Two SATA onboard connectors
- 2 UART
- JTAG support
- QSPI emulator support
- TDM riser support
QDS Default Switch Settings (1: ON; 0: OFF)
-------------------------------------------
For 16b IFC-NOR
SW1 0001 0010
SW2 x110 1111
For QSPI Boot
SW1 0011 0001
SW2 0110 1111
For SD Boot
SW1 0010 0000
SW2 0110 1111
For eMMC Boot
SW1 0010 0000
SW2 1110 1111
For I2C (ext. addr.)
SW1 0010 0100
SW2 1110 1111
SW3 to SW12 are identical for all boot source
SW3 0010 0100
SW4 0010 0000
SW5 1110 0111
SW6 1110 1000
SW7 0001 1101
SW8 0000 1101
SW9 1100 1010
SW10 1110 1000
SW11 1111 0100
SW12 1111 1111
LS1088AQDS board Overview
-------------------------
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
- SATA 3.0
- 2 XFI
- QSGMII, SGMII with help for Riser card
- 2 RGMII
- 5 slot for Riser card or PCIe NIC
- DDR Controller
- One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
with FSL refernce software is 2100MT/s
- 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
- IFC/Local Bus
- One 2 GB NAND flash with ECC support, not as boot source
- CPLD of size 2K
- USB 3.0
- Two high speed USB 3.0 ports
- First USB 3.0 port configured as Host with Type-A connector
- Second USB 3.0 port configured as OTG with micro-AB connector
- SDHC/eMMC
- SDHC/eMMC slot via adaptor
- 4 I2C controllers
- Two SATA onboard connectors
- 2 UART
- JTAG support
- DSPI
- PROMJET support
- QSPI emulator support
- TDM riser support
QSPI flash memory map valid for both QDS and RDB
Image Flash Offset
RCW+PBI 0x00000000
Boot firmware (U-Boot) 0x00100000
Boot firmware Environment 0x00300000
PPA firmware 0x00400000
DPAA2 MC 0x00A00000
DPAA2 DPL 0x00D00000
DPAA2 DPC 0x00E00000
Kernel.itb 0x01000000