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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
178 lines
3.6 KiB
C
178 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2009-2013 Freescale Semiconductor, Inc.
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* Copyright 2021 NXP
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*/
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#include <common.h>
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#include <command.h>
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#include <env.h>
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#include <fdt_support.h>
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#include <i2c.h>
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#include <image.h>
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#include <init.h>
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#include <netdev.h>
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#include <asm/global_data.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include "t208xrdb.h"
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#include "cpld.h"
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#include "../common/vid.h"
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DECLARE_GLOBAL_DATA_PTR;
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u8 get_hw_revision(void)
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{
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u8 ver = CPLD_READ(hw_ver);
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switch (ver) {
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default:
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case 0x1:
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return 'C';
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case 0x0:
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return 'D';
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case 0x2:
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return 'E';
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}
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}
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int checkboard(void)
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{
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struct cpu_type *cpu = gd->arch.cpu;
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static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
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printf("Board: %sRDB, ", cpu->name);
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printf("Board rev: %c CPLD ver: 0x%02x, boot from ",
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get_hw_revision(), CPLD_READ(sw_ver));
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#ifdef CONFIG_SDCARD
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puts("SD/MMC\n");
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#elif CONFIG_SPIFLASH
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puts("SPI\n");
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#else
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u8 reg;
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reg = CPLD_READ(flash_csr);
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if (reg & CPLD_BOOT_SEL) {
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puts("NAND\n");
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} else {
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reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
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printf("NOR vBank%d\n", reg);
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}
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#endif
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puts("SERDES Reference Clocks:\n");
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printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
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printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
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return 0;
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CFG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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/*
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* Adjust core voltage according to voltage ID
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* This function changes I2C mux to channel 2.
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*/
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if (adjust_vdd(0))
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printf("Warning: Adjusting core voltage failed.\n");
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return 0;
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}
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int misc_init_r(void)
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{
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u8 reg;
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/* Reset CS4315 PHY */
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reg = CPLD_READ(reset_ctl);
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reg |= CPLD_RSTCON_EDC_RST;
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CPLD_WRITE(reset_ctl, reg);
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/* Enable POR for boards revisions D and up */
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if (get_hw_revision() >= 'D') {
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reg = CPLD_READ(misc_csr);
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reg |= CPLD_MISC_POR_EN;
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CPLD_WRITE(misc_csr, reg);
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}
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return 0;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = env_get_bootm_low();
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size = env_get_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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fsl_fdt_fixup_dr_usb(blob, bd);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_board_fman_ethernet(blob);
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fdt_fixup_board_enet(blob);
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fdt_fixup_board_phy(blob);
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#endif
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return 0;
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}
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ulong *cs4340_get_fw_addr(void)
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{
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ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
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#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR
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u8 reg;
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reg = CPLD_READ(flash_csr);
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if (!(reg & CPLD_BOOT_SEL)) {
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reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
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if (reg == 0)
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cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
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else if (reg == 4)
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cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
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}
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#endif
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return (ulong *)cortina_fw_addr;
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}
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