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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
437 lines
10 KiB
C
437 lines
10 KiB
C
/*
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* Freescale i.MX23/i.MX28 clock setup code
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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/*
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* The PLL frequency is 480MHz and XTAL frequency is 24MHz
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* iMX23: datasheet section 4.2
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* iMX28: datasheet section 10.2
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*/
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#define PLL_FREQ_KHZ 480000
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#define PLL_FREQ_COEF 18
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#define XTAL_FREQ_KHZ 24000
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#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
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#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
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#if defined(CONFIG_MX23)
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#define MXC_SSPCLK_MAX MXC_SSPCLK0
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#elif defined(CONFIG_MX28)
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#define MXC_SSPCLK_MAX MXC_SSPCLK3
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#endif
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static uint32_t mxs_get_pclk(void)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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uint32_t clkctrl, clkseq, div;
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uint8_t clkfrac, frac;
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clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
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/* No support of fractional divider calculation */
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if (clkctrl &
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(CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
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return 0;
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}
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clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
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/* XTAL Path */
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if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) {
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div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >>
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CLKCTRL_CPU_DIV_XTAL_OFFSET;
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return XTAL_FREQ_MHZ / div;
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}
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/* REF Path */
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clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
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frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
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div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
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return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
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}
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static uint32_t mxs_get_hclk(void)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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uint32_t div;
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uint32_t clkctrl;
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clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus);
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/* No support of fractional divider calculation */
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if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN)
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return 0;
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div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
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return mxs_get_pclk() / div;
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}
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static uint32_t mxs_get_emiclk(void)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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uint32_t clkctrl, clkseq, div;
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uint8_t clkfrac, frac;
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clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
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clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);
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/* XTAL Path */
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if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) {
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div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >>
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CLKCTRL_EMI_DIV_XTAL_OFFSET;
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return XTAL_FREQ_MHZ / div;
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}
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/* REF Path */
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clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
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frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
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div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
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return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
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}
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static uint32_t mxs_get_gpmiclk(void)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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#if defined(CONFIG_MX23)
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uint8_t *reg =
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&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
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#elif defined(CONFIG_MX28)
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uint8_t *reg =
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&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
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#endif
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uint32_t clkctrl, clkseq, div;
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uint8_t clkfrac, frac;
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clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
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clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
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/* XTAL Path */
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if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) {
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div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
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return XTAL_FREQ_MHZ / div;
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}
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/* REF Path */
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clkfrac = readb(reg);
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frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
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div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
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return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
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}
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/*
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* Set IO clock frequency, in kHz
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*/
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void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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uint32_t div;
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int io_reg;
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if (freq == 0)
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return;
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if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
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return;
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div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;
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if (div < 18)
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div = 18;
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if (div > 35)
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div = 35;
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io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */
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writeb(CLKCTRL_FRAC_CLKGATE,
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&clkctrl_regs->hw_clkctrl_frac0_set[io_reg]);
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writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK),
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&clkctrl_regs->hw_clkctrl_frac0[io_reg]);
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writeb(CLKCTRL_FRAC_CLKGATE,
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&clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]);
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}
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/*
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* Get IO clock, returns IO clock in kHz
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*/
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static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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uint8_t ret;
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int io_reg;
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if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
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return 0;
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io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */
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ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) &
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CLKCTRL_FRAC_FRAC_MASK;
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return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
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}
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/*
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* Configure SSP clock frequency, in kHz
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*/
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void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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uint32_t clk, clkreg;
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if (ssp > MXC_SSPCLK_MAX)
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return;
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clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
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(ssp * sizeof(struct mxs_register_32));
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clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
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while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
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;
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if (xtal)
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clk = XTAL_FREQ_KHZ;
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else
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clk = mxs_get_ioclk(ssp >> 1);
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if (freq > clk)
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return;
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/* Calculate the divider and cap it if necessary */
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clk /= freq;
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if (clk > CLKCTRL_SSP_DIV_MASK)
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clk = CLKCTRL_SSP_DIV_MASK;
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clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk);
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while (readl(clkreg) & CLKCTRL_SSP_BUSY)
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;
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if (xtal)
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writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
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&clkctrl_regs->hw_clkctrl_clkseq_set);
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else
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writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
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&clkctrl_regs->hw_clkctrl_clkseq_clr);
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}
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/*
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* Return SSP frequency, in kHz
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*/
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static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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uint32_t clkreg;
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uint32_t clk, tmp;
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if (ssp > MXC_SSPCLK_MAX)
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return 0;
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tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
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if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp))
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return XTAL_FREQ_KHZ;
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clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
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(ssp * sizeof(struct mxs_register_32));
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tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
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if (tmp == 0)
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return 0;
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clk = mxs_get_ioclk(ssp >> 1);
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return clk / tmp;
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}
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/*
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* Set SSP/MMC bus frequency, in kHz)
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*/
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void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
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{
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struct mxs_ssp_regs *ssp_regs;
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const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus);
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const uint32_t sspclk = mxs_get_sspclk(clk);
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uint32_t reg;
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uint32_t divide, rate, tgtclk;
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ssp_regs = mxs_ssp_regs_by_bus(bus);
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/*
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* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
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* CLOCK_DIVIDE has to be an even value from 2 to 254, and
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* CLOCK_RATE could be any integer from 0 to 255.
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*/
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for (divide = 2; divide < 254; divide += 2) {
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rate = sspclk / freq / divide;
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if (rate <= 256)
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break;
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}
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tgtclk = sspclk / divide / rate;
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while (tgtclk > freq) {
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rate++;
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tgtclk = sspclk / divide / rate;
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}
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if (rate > 256)
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rate = 256;
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/* Always set timeout the maximum */
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reg = SSP_TIMING_TIMEOUT_MASK |
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(divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) |
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((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET);
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writel(reg, &ssp_regs->hw_ssp_timing);
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debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n",
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bus, tgtclk, freq);
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}
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void mxs_set_lcdclk(uint32_t freq)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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uint32_t fp, x, k_rest, k_best, x_best, tk;
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int32_t k_best_l = 999, k_best_t = 0, x_best_l = 0xff, x_best_t = 0xff;
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if (freq == 0)
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return;
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#if defined(CONFIG_MX23)
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writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);
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#elif defined(CONFIG_MX28)
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writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);
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#endif
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/*
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* / 18 \ 1 1
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* freq kHz = | 480000000 Hz * -- | * --- * ------
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* \ x / k 1000
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*
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* 480000000 Hz 18
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* ------------ * --
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* freq kHz x
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* k = -------------------
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* 1000
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*/
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fp = ((PLL_FREQ_KHZ * 1000) / freq) * 18;
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for (x = 18; x <= 35; x++) {
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tk = fp / x;
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if ((tk / 1000 == 0) || (tk / 1000 > 255))
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continue;
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k_rest = tk % 1000;
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if (k_rest < (k_best_l % 1000)) {
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k_best_l = tk;
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x_best_l = x;
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}
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if (k_rest > (k_best_t % 1000)) {
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k_best_t = tk;
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x_best_t = x;
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}
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}
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if (1000 - (k_best_t % 1000) > (k_best_l % 1000)) {
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k_best = k_best_l;
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x_best = x_best_l;
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} else {
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k_best = k_best_t;
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x_best = x_best_t;
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}
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k_best /= 1000;
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#if defined(CONFIG_MX23)
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writeb(CLKCTRL_FRAC_CLKGATE,
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&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);
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writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
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&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]);
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writeb(CLKCTRL_FRAC_CLKGATE,
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&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]);
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writel(CLKCTRL_PIX_CLKGATE,
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&clkctrl_regs->hw_clkctrl_pix_set);
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clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix,
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CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE,
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k_best << CLKCTRL_PIX_DIV_OFFSET);
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while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
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;
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#elif defined(CONFIG_MX28)
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writeb(CLKCTRL_FRAC_CLKGATE,
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&clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);
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writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
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&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_PIX]);
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writeb(CLKCTRL_FRAC_CLKGATE,
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&clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]);
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writel(CLKCTRL_DIS_LCDIF_CLKGATE,
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&clkctrl_regs->hw_clkctrl_lcdif_set);
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clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif,
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CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE,
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k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET);
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while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY)
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;
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#endif
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}
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uint32_t mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_ARM_CLK:
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return mxs_get_pclk() * 1000000;
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case MXC_GPMI_CLK:
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return mxs_get_gpmiclk() * 1000000;
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case MXC_AHB_CLK:
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case MXC_IPG_CLK:
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return mxs_get_hclk() * 1000000;
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case MXC_EMI_CLK:
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return mxs_get_emiclk();
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case MXC_IO0_CLK:
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return mxs_get_ioclk(MXC_IOCLK0);
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case MXC_IO1_CLK:
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return mxs_get_ioclk(MXC_IOCLK1);
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case MXC_XTAL_CLK:
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return XTAL_FREQ_KHZ * 1000;
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case MXC_SSP0_CLK:
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return mxs_get_sspclk(MXC_SSPCLK0);
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#ifdef CONFIG_MX28
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case MXC_SSP1_CLK:
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return mxs_get_sspclk(MXC_SSPCLK1);
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case MXC_SSP2_CLK:
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return mxs_get_sspclk(MXC_SSPCLK2);
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case MXC_SSP3_CLK:
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return mxs_get_sspclk(MXC_SSPCLK3);
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#endif
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}
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return 0;
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}
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