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73d2de2b59
If SPL is used we want to use the generic SPL framework and boot from SPI via a board-specific means. Add these options to the board config file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
66 lines
1.5 KiB
C
66 lines
1.5 KiB
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <configs/x86-common.h>
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#define CONFIG_SYS_MONITOR_LEN (1 << 20)
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#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \
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"stdout=serial,vidconsole\0" \
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"stderr=serial,vidconsole\0"
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/*
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* ATA/SATA support for QEMU x86 targets
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* - Only legacy IDE controller is supported for QEMU '-M pc' target
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* - AHCI controller is supported for QEMU '-M q35' target
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*
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* Default configuraion is to support the QEMU default x86 target
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* Undefine CONFIG_CMD_IDE to support q35 target
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*/
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#define CONFIG_CMD_IDE
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#ifdef CONFIG_CMD_IDE
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#define CONFIG_SYS_IDE_MAXBUS 2
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#define CONFIG_SYS_IDE_MAXDEVICE 4
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#define CONFIG_SYS_ATA_BASE_ADDR 0
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#define CONFIG_SYS_ATA_DATA_OFFSET 0
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#define CONFIG_SYS_ATA_REG_OFFSET 0
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#define CONFIG_SYS_ATA_ALT_OFFSET 0
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
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#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
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#define CONFIG_ATAPI
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#undef CONFIG_SCSI_AHCI
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#undef CONFIG_SCSI
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#else
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#define CONFIG_SCSI_DEV_LIST \
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI}
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#endif
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/* GPIO is not supported */
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#undef CONFIG_INTEL_ICH6_GPIO
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/* SPI is not supported */
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#undef CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0xfffd0000
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#define BOOT_DEVICE_SPI 10
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#define CONFIG_SPL_BOARD_LOAD_IMAGE
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#define BOOT_DEVICE_BOARD 11
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#endif /* __CONFIG_H */
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