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The 'xtfpga' board is actually a set of FPGA evaluation boards that can be configured to run an Xtensa processor. - Avnet Xilinx LX60 - Avnet Xilinx LX110 - Avnet Xilinx LX200 - Xilinx ML605 - Xilinx KC705 These boards share the same components (open-ethernet, ns16550 serial, lcd display, flash, etc.). Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
126 lines
4.7 KiB
Plaintext
126 lines
4.7 KiB
Plaintext
Tensilica 'xtfpga' Evaluation Boards
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====================================
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Tensilica's 'xtfpga' evaluation boards are actually a set of different
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boards that share configurations. The following is a list of supported
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hardware by this board type:
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- XT-AV60 / LX60
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- XT-AV110 / LX110
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- XT-AV200 / LX200
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- ML605
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- KC705
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All boards provide the following common configurations:
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- An Xtensa or Diamond processor core.
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- An on-chip-debug (OCD) JTAG interface.
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- A 16550 compatible UART and serial port.
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- An OpenCores Wishbone 10/100-base-T ethernet interface.
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- A 32 char two line LCD display. (except for the LX200)
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LX60/LX110/LX200:
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- Virtex-4 (XC4VLX60 / XCV4LX200) / Virtext-5 (XC5VLX110)
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- 128MB / 64MB (LX60) memory
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- 16MB / 4MB (LX60) Linear Flash
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ML605
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- Virtex-6 (XC6VLX240T)
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- 512MB DDR3 memory
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- 16MB Linear BPI Flash
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KC705 (Xilinx)
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- Kintex-7 XC7K325T FPGA
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- 1GB DDR3 memory
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- 128MB Linear BPI Flash
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Setting up the Board
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--------------------
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The serial port defaults to 115200 baud, no parity and 1 stop bit.
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A terminal emulator must be set accordingly to see the U-Boot prompt.
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Board Configurations LX60/LX110/LX200/ML605/KC705
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-------------------------------------------------
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The LX60/LX110/LX200/ML605 contain an 8-way DIP switch that controls
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the boot mapping and selects from a range of default ethernet MAC
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addresses.
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Boot Mapping (DIP switch 8):
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DIP switch 8 maps the system ROM address space (in which the
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reset vector resides) to either SRAM (off, 0, down) or Flash
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(on, 1, up). This mapping is implemented in the FPGA bitstream
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and cannot be disabled by software, therefore DIP switch 8 is no
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available for application use. Note DIP switch 7 is reserved by
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Tensilica for future possible hardware use.
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Mapping to SRAM allows U-Boot to be debugged with an OCD/JTAG
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tool such as the Xtensa OCD Daemon connected via a suppored probe.
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See the tools documentation for supported probes and how to
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connect them. Be aware that the board has only 128 KB of SRAM,
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therefore U-Boot must fit within this space to debug an image
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intended for the Flash. This issues is discussed in a separate
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section toward the end.
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Mapping to flash allows U-Boot to start on reset, provided it
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has been programmed into the first two 64 KB sectors of the Flash.
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The Flash is always mapped at a device (memory mapped I/O) address
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(the address is board specific and is expressed as CFG_FLASH_BASE).
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The device address is used by U-Boot to program the flash, and may
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be used to specify an application to run or U-Boot image to boot.
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Default MAC Address (DIP switches 1-6):
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When the board is first powered on, or after the environment has
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been reinitialized, the ethernet MAC address receives a default
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value whose least significant 6 bits come from DIP switches 1-6.
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The default is 00:50:C2:13:6F:xx where xx ranges from 0..3F
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according to the DIP switches, where "on"==1 and "off"==0, and
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switch 1 is the least-significant bit.
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After initial startup, the MAC address is stored in the U-Boot
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environment variable 'ethaddr'. The user may change this to any
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other address with the "setenv" comamnd. After the environment
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has been saved to Flash by the "saveenv" command, this will be
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used and the DIP switches no longer consulted. DIP swithes 1-6
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may then be used for application purposes.
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The KC705 board contains 4-way DIP switch, way 1 is the boot mapping
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switch and ways 2-4 control the low three bits of the MAC address.
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Limitation of SDRAM Size for OCD Debugging on the LX60
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------------------------------------------------------
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The XT-AV60 board has only 128 KB of SDRAM that can be mapped
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to the system ROM address space for debugging a ROM image under
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OCD/JTAG. This limits the useful size of U-Boot to 128 KB (0x20000)
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or the first 2 sectors of the flash.
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This can pose a problem if all the sources are compiled with -O0
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for debugging. The code size is then too large, in which case it
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would be necessary to temporarily alter the linker script to place
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the load addresses (LMA) in the RAM (VMA) so that OCD loads U-Boot
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directly there and does not unpack. In practice this is not really
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necessary as long as only a limited set of sources need to be
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debugged, because the image can still fit into the 128 KB SRAM.
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The recommended procedure for debugging is to first build U-Boot
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with the default optimization level (-Os), and then touch and
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rebuild incrementally with -O0 so that only the touched sources
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are recompiled with -O0. To build with -O0, pass it in the KCFLAGS
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variable to make.
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Because this problem is easy to fall into and difficult to debug
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if one doesn't expect it, the linker script provides a link-time
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check and fatal error message if the image size exceeds 128 KB.
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