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https://github.com/u-boot/u-boot.git
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fa82f871c8
There was a mix of UTF-8 and ISO-8859 files in the U-Boot source tree, which could cause issues with the patchwork review system. This commit converts all ISO-8859 files to UTF-8. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
89 lines
2.8 KiB
C
89 lines
2.8 KiB
C
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* i8259.h i8259 PIC Registers */
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#ifndef _ASMI386_I8259_H_
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#define _ASMI386_I8959_H_ 1
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/* PIC I/O mapped registers */
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#define IRR 0x0 /* Interrupt Request Register */
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#define ISR 0x0 /* In-Service Register */
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#define ICW1 0x0 /* Initialization Control Word 1 */
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#define OCW2 0x0 /* Operation Control Word 2 */
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#define OCW3 0x0 /* Operation Control Word 3 */
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#define ICW2 0x1 /* Initialization Control Word 2 */
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#define ICW3 0x1 /* Initialization Control Word 3 */
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#define ICW4 0x1 /* Initialization Control Word 4 */
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#define IMR 0x1 /* Interrupt Mask Register */
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/* bits for IRR, IMR, ISR and ICW3 */
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#define IR7 0x80 /* IR7 */
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#define IR6 0x40 /* IR6 */
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#define IR5 0x20 /* IR5 */
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#define IR4 0x10 /* IR4 */
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#define IR3 0x08 /* IR3 */
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#define IR2 0x04 /* IR2 */
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#define IR1 0x02 /* IR1 */
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#define IR0 0x01 /* IR0 */
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/* bits for SEOI */
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#define SEOI_IR7 0x07 /* IR7 */
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#define SEOI_IR6 0x06 /* IR6 */
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#define SEOI_IR5 0x05 /* IR5 */
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#define SEOI_IR4 0x04 /* IR4 */
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#define SEOI_IR3 0x03 /* IR3 */
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#define SEOI_IR2 0x02 /* IR2 */
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#define SEOI_IR1 0x01 /* IR1 */
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#define SEOI_IR0 0x00 /* IR0 */
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/* OCW2 bits */
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#define OCW2_RCLR 0x00 /* Rotate/clear */
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#define OCW2_NEOI 0x20 /* Non specific EOI */
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#define OCW2_NOP 0x40 /* NOP */
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#define OCW2_SEOI 0x60 /* Specific EOI */
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#define OCW2_RSET 0x80 /* Rotate/set */
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#define OCW2_REOI 0xA0 /* Rotate on non specific EOI */
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#define OCW2_PSET 0xC0 /* Priority Set Command */
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#define OCW2_RSEOI 0xE0 /* Rotate on specific EOI */
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/* ICW1 bits */
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#define ICW1_SEL 0x10 /* Select ICW1 */
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#define ICW1_LTIM 0x08 /* Level-Triggered Interrupt Mode */
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#define ICW1_ADI 0x04 /* Address Interval */
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#define ICW1_SNGL 0x02 /* Single PIC */
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#define ICW1_EICW4 0x01 /* Expect initilization ICW4 */
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/* ICW2 is the starting vector number */
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/* ICW2 is bit-mask of present slaves for a master device,
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* or the slave ID for a slave device */
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/* ICW4 bits */
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#define ICW4_AEOI 0x02 /* Automatic EOI Mode */
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#define ICW4_PM 0x01 /* Microprocessor Mode */
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#endif
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