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349 lines
9.9 KiB
C
349 lines
9.9 KiB
C
/*
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**=====================================================================
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**
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** Copyright (C) 2000, 2001, 2002, 2003
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** The LEOX team <team@leox.org>, http://www.leox.org
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**
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** LEOX.org is about the development of free hardware and software resources
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** for system on chip.
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**
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** Description: U-Boot port on the LEOX's ELPT860 CPU board
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** ~~~~~~~~~~~
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**
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**=====================================================================
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**
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** This program is free software; you can redistribute it and/or
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** modify it under the terms of the GNU General Public License as
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** published by the Free Software Foundation; either version 2 of
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** the License, or (at your option) any later version.
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**
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** This program is distributed in the hope that it will be useful,
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** but WITHOUT ANY WARRANTY; without even the implied warranty of
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** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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** GNU General Public License for more details.
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**
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** You should have received a copy of the GNU General Public License
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** along with this program; if not, write to the Free Software
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** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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** MA 02111-1307 USA
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**
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**=====================================================================
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*/
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/*
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** Note 1: In this file, you have to provide the following functions:
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** ------
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** int board_early_init_f(void)
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** int checkboard(void)
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** long int initdram(int board_type)
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** called from 'board_init_f()' into 'common/board.c'
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**
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** void reset_phy(void)
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** called from 'board_init_r()' into 'common/board.c'
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*/
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#include <common.h>
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#include <mpc8xx.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint init_sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
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0xFFFFFC04, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
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0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
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0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
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};
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
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0xFF0FFC00, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
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0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
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0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
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0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
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0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
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_NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
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0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
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0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
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0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
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0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
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};
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/* ------------------------------------------------------------------------- */
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#define CFG_PC4 0x0800
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#define CFG_DS1 CFG_PC4
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/*
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* Very early board init code (fpga boot, etc.)
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*/
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int board_early_init_f (void)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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/*
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* Light up the red led on ELPT860 pcb (DS1) (PCDAT)
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*/
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immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */
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immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */
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immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */
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return (0); /* success */
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}
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/*
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* Check Board Identity:
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*
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* Test ELPT860 ID string
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*
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* Return 1 if no second DRAM bank, otherwise returns 0
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*/
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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if (!s || strncmp (s, "ELPT860", 7))
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printf ("### No HW ID - assuming ELPT860\n");
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return (0); /* success */
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size8, size9;
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long int size_b0 = 0;
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/*
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* This sequence initializes SDRAM chips on ELPT860 board
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*/
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upmconfig (UPMA, (uint *) init_sdram_table,
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sizeof (init_sdram_table) / sizeof (uint));
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memctl->memc_mptpr = 0x0200;
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memctl->memc_mamr = 0x18002111;
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memctl->memc_mar = 0x00000088;
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memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
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/*
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* The following value is used as an address (i.e. opcode) for
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* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
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* the port size is 32bit the SDRAM does NOT "see" the lower two
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* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
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* MICRON SDRAMs:
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* -> 0 00 010 0 010
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* | | | | +- Burst Length = 4
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* | | | +----- Burst Type = Sequential
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* | | +------- CAS Latency = 2
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* | +----------- Operating Mode = Standard
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* +-------------- Write Burst Mode = Programmed Burst Length
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*/
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or1 = CFG_OR1_PRELIM;
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memctl->memc_br1 = CFG_BR1_PRELIM;
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memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */
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udelay (1);
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memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */
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udelay (1);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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* try 8 column mode
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*/
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size8 = dram_size (CFG_MAMR_8COL,
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SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
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udelay (1000);
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/*
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* try 9 column mode
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*/
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size9 = dram_size (CFG_MAMR_9COL,
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SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
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if (size8 < size9) { /* leave configuration at 9 columns */
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size_b0 = size9;
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/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
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} else { /* back to 8 columns */
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size_b0 = size8;
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memctl->memc_mamr = CFG_MAMR_8COL;
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udelay (500);
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/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
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}
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udelay (1000);
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/*
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* Adjust refresh rate depending on SDRAM type, both banks
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* For types > 128 MBit leave it at the current (fast) rate
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*/
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if (size_b0 < 0x02000000) {
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/* reduce to 15.6 us (62.4 us / quad) */
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memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
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udelay (1000);
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}
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/*
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* Final mapping: map bigger bank first
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*/
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memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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{
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unsigned long reg;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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}
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udelay (10000);
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return (size_b0);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int
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dram_size (long int mamr_value, long int *base, long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size (base, maxsize));
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}
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/* ------------------------------------------------------------------------- */
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#define CFG_PA1 0x4000
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#define CFG_PA2 0x2000
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#define CFG_LBKs (CFG_PA2 | CFG_PA1)
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void reset_phy (void)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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/*
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* Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
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* and no AUI loopback
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*/
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immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */
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immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */
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immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */
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}
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