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a43d46a73c
Cache maintenance procedure is same for v7A and v7R processors. So re-use cache-cp15.c file except for mmu parts. Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
120 lines
2.6 KiB
C
120 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Cortex-R Memory Protection Unit specific code
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/armv7.h>
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#include <asm/system.h>
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#include <asm/barriers.h>
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#include <linux/compiler.h>
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#include <asm/armv7_mpu.h>
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/* MPU Type register definitions */
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#define MPUIR_S_SHIFT 0
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#define MPUIR_S_MASK BIT(MPUIR_S_SHIFT)
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#define MPUIR_DREGION_SHIFT 8
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#define MPUIR_DREGION_MASK (0xff << 8)
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/**
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* Note:
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* The Memory Protection Unit(MPU) allows to partition memory into regions
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* and set individual protection attributes for each region. In absence
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* of MPU a default map[1] will take effect. make sure to run this code
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* from a region which has execution permissions by default.
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* [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I1002400.html
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*/
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void disable_mpu(void)
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{
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u32 reg;
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reg = get_cr();
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reg &= ~CR_M;
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dsb();
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set_cr(reg);
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isb();
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}
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void enable_mpu(void)
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{
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u32 reg;
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reg = get_cr();
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reg |= CR_M;
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dsb();
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set_cr(reg);
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isb();
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}
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int mpu_enabled(void)
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{
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return get_cr() & CR_M;
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}
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void mpu_config(struct mpu_region_config *rgn)
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{
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u32 attr, val;
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attr = get_attr_encoding(rgn->mr_attr);
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/* MPU Region Number Register */
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asm volatile ("mcr p15, 0, %0, c6, c2, 0" : : "r" (rgn->region_no));
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/* MPU Region Base Address Register */
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asm volatile ("mcr p15, 0, %0, c6, c1, 0" : : "r" (rgn->start_addr));
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/* MPU Region Size and Enable Register */
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if (rgn->reg_size)
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val = (rgn->reg_size << REGION_SIZE_SHIFT) | ENABLE_REGION;
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else
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val = DISABLE_REGION;
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asm volatile ("mcr p15, 0, %0, c6, c1, 2" : : "r" (val));
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/* MPU Region Access Control Register */
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val = rgn->xn << XN_SHIFT | rgn->ap << AP_SHIFT | attr;
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asm volatile ("mcr p15, 0, %0, c6, c1, 4" : : "r" (val));
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}
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void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns)
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{
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u32 num, i;
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asm volatile ("mrc p15, 0, %0, c0, c0, 4" : "=r" (num));
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num = (num & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT;
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/* Regions to be configured cannot be greater than available regions */
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if (num < num_rgns)
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num_rgns = num;
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/**
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* Assuming dcache might not be enabled at this point, disabling
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* and invalidating only icache.
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*/
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icache_disable();
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invalidate_icache_all();
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disable_mpu();
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for (i = 0; i < num_rgns; i++)
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mpu_config(&rgns[i]);
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enable_mpu();
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icache_enable();
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}
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void enable_caches(void)
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{
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/*
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* setup_mpu_regions() might have enabled Icache. So add a check
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* before enabling Icache
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*/
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if (!icache_status())
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icache_enable();
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dcache_enable();
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}
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