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95c69223f9
Extend the documentation of the fec_mxc configuration by describing its ability to read the ethaddr MAC address from the SoC eFuses. Also add an example how to program the fuses for an imx5 to clarify the byte order. Cc: Stefano Babic <sbabic at denx.de> Cc: Marek Vasut <marex at denx.de> Signed-off-by: Olaf Mandel <o.mandel at menlosystems.com>
35 lines
1.1 KiB
Plaintext
35 lines
1.1 KiB
Plaintext
U-boot config options used in fec_mxc.c
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CONFIG_FEC_MXC
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Selects fec_mxc.c to be compiled into u-boot. Can read out the
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ethaddr from the SoC eFuses (see below).
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CONFIG_MII
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Must be defined if CONFIG_FEC_MXC is defined.
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CONFIG_FEC_XCV_TYPE
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Defaults to MII100 for 100 Base-tx.
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RGMII selects 1000 Base-tx reduced pin count interface.
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RMII selects 100 Base-tx reduced pin count interface.
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CONFIG_FEC_MXC_SWAP_PACKET
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Forced on iff MX28.
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Swaps the bytes order of all words(4 byte units) in the packet.
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This should not be specified by a board file. It is cpu specific.
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CONFIG_PHYLIB
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fec_mxc supports PHYLIB and should be used for new boards.
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CONFIG_FEC_MXC_NO_ANEG
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Relevant only if PHYLIB not used. Skips auto-negotiation restart.
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CONFIG_FEC_MXC_PHYADDR
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Optional, selects the exact phy address that should be connected
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and function fecmxc_initialize will try to initialize it.
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Reading the ethaddr from the SoC eFuses:
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if CONFIG_FEC_MXC is defined and the U-Boot environment does not contain the
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ethaddr variable, then its value gets read from the corresponding eFuses in
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the SoC. See the README files of the specific SoC for details.
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