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d021e94210
This converts the following to Kconfig: CONFIG_BOOTP_BOOTPATH CONFIG_BOOTP_DNS CONFIG_BOOTP_GATEWAY CONFIG_BOOTP_HOSTNAME CONFIG_BOOTP_PXE CONFIG_BOOTP_SUBNETMASK CONFIG_CMDLINE_EDITING CONFIG_AUTO_COMPLETE CONFIG_SYS_LONGHELP CONFIG_SUPPORT_RAW_INITRD CONFIG_ENV_VARS_UBOOT_CONFIG Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Re-run the migration] Signed-off-by: Tom Rini <trini@konsulko.com>
129 lines
3.4 KiB
C
129 lines
3.4 KiB
C
/*
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* (C) Copyright 2010
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* Ilko Iliev <iliev@ronetix.at>
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* Asen Dimov <dimov@ronetix.at>
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* Ronetix GmbH <www.ronetix.at>
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*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* Configuation settings for the PM9G45 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* SoC must be defined first, before hardware.h is included.
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* In this case SoC is defined in boards.cfg.
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*/
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#include <asm/hardware.h>
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#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */
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#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45"
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#define CONFIG_MACH_TYPE MACH_TYPE_PM9G45
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/*
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* Hardware drivers
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*/
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#define CONFIG_AT91_GPIO 1
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#define CONFIG_ATMEL_USART 1
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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#define CONFIG_SYS_USE_NANDFLASH 1
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/* LED */
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#define CONFIG_AT91_LED
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#define CONFIG_RED_LED GPIO_PIN_PD(31) /* this is the user1 led */
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#define CONFIG_GREEN_LED GPIO_PIN_PD(0) /* this is the user2 led */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE 1
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#define CONFIG_JFFS2_CMDLINE 1
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#define CONFIG_JFFS2_NAND 1
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#define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */
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#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
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#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x70000000
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#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
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#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(3)
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#endif
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/* Ethernet */
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#define CONFIG_MACB 1
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#define CONFIG_RMII 1
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_RESET_PHY_R 1
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/* USB */
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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/* board specific(not enough SRAM) */
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#define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000
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#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE
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/* bootstrap + u-boot + env + linux in nandflash */
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#define CONFIG_ENV_OFFSET 0x60000
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#define CONFIG_ENV_OFFSET_REDUND 0x80000
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#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
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#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm"
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
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0x1000)
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
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GENERATED_GBL_DATA_SIZE)
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#endif
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