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86b8e7d61a
Add GPIO driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
135 lines
3.6 KiB
C
135 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#define P(bank) (0x0000 + (bank) * 4)
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#define PSR(bank) (0x0100 + (bank) * 4)
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#define PPR(bank) (0x0200 + (bank) * 4)
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#define PM(bank) (0x0300 + (bank) * 4)
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#define PMC(bank) (0x0400 + (bank) * 4)
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#define PFC(bank) (0x0500 + (bank) * 4)
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#define PFCE(bank) (0x0600 + (bank) * 4)
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#define PNOT(bank) (0x0700 + (bank) * 4)
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#define PMSR(bank) (0x0800 + (bank) * 4)
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#define PMCSR(bank) (0x0900 + (bank) * 4)
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#define PFCAE(bank) (0x0A00 + (bank) * 4)
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#define PIBC(bank) (0x4000 + (bank) * 4)
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#define PBDC(bank) (0x4100 + (bank) * 4)
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#define PIPC(bank) (0x4200 + (bank) * 4)
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#define RZA1_MAX_GPIO_PER_BANK 16
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DECLARE_GLOBAL_DATA_PTR;
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struct r7s72100_gpio_priv {
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void __iomem *regs;
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int bank;
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};
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static int r7s72100_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
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return !!(readw(priv->regs + PPR(priv->bank)) & BIT(offset));
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}
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static int r7s72100_gpio_set_value(struct udevice *dev, unsigned line,
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int value)
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{
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struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
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writel(BIT(line + 16) | (value ? BIT(line) : 0),
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priv->regs + PSR(priv->bank));
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return 0;
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}
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static void r7s72100_gpio_set_direction(struct udevice *dev, unsigned line,
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bool output)
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{
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struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
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writel(BIT(line + 16), priv->regs + PMCSR(priv->bank));
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writel(BIT(line + 16) | (output ? 0 : BIT(line)),
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priv->regs + PMSR(priv->bank));
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clrsetbits_le16(priv->regs + PIBC(priv->bank), BIT(line),
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output ? 0 : BIT(line));
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}
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static int r7s72100_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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r7s72100_gpio_set_direction(dev, offset, false);
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return 0;
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}
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static int r7s72100_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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/* write GPIO value to output before selecting output mode of pin */
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r7s72100_gpio_set_value(dev, offset, value);
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r7s72100_gpio_set_direction(dev, offset, true);
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return 0;
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}
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static int r7s72100_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
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if (readw(priv->regs + PM(priv->bank)) & BIT(offset))
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return GPIOF_INPUT;
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else
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return GPIOF_OUTPUT;
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}
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static const struct dm_gpio_ops r7s72100_gpio_ops = {
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.direction_input = r7s72100_gpio_direction_input,
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.direction_output = r7s72100_gpio_direction_output,
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.get_value = r7s72100_gpio_get_value,
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.set_value = r7s72100_gpio_set_value,
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.get_function = r7s72100_gpio_get_function,
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};
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static int r7s72100_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
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struct fdtdec_phandle_args args;
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int node = dev_of_offset(dev);
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int ret;
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fdt_addr_t addr_base;
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uc_priv->bank_name = dev->name;
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dev = dev_get_parent(dev);
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addr_base = devfdt_get_addr(dev);
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if (addr_base == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = (void __iomem *)addr_base;
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ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
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NULL, 3, 0, &args);
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priv->bank = ret == 0 ? (args.args[1] / RZA1_MAX_GPIO_PER_BANK) : -1;
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uc_priv->gpio_count = ret == 0 ? args.args[2] : RZA1_MAX_GPIO_PER_BANK;
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return 0;
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}
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U_BOOT_DRIVER(r7s72100_gpio) = {
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.name = "r7s72100-gpio",
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.id = UCLASS_GPIO,
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.ops = &r7s72100_gpio_ops,
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.priv_auto_alloc_size = sizeof(struct r7s72100_gpio_priv),
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.probe = r7s72100_gpio_probe,
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};
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