mirror of
https://github.com/u-boot/u-boot.git
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a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
878 lines
20 KiB
Plaintext
878 lines
20 KiB
Plaintext
# Porting U-Boot onto RPXlite board
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# Written by Yoo. Jonghoon
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# E-Mail : yooth@ipone.co.kr
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# IP ONE Inc.
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# Since 2001. 1. 29
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# Shell : bash
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# Cross-compile tools : Montavista Hardhat
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# Debugging tools : Windriver VisionProbe (PowerPC BDM)
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# ppcboot ver. : ppcboot-0.8.1
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###############################################################
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# 1. Hardware setting
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###############################################################
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1.1. Board, BDM settings
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Install board, BDM, connect each other
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1.2. Save Register value
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Boot with board-on monitor program and save the
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register values with BDM.
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1.3. Configure flash programmer
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Check flash memory area in the memory map.
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0xFFC00000 - 0xFFFFFFFF
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Boot monitor program is at
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0xFFF00000
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You can program on-board flash memory with VisionClick
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flash programmer. Set the target flash device as:
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29DL800B
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(?) The flash memory device in the board *is* 29LV800B,
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but I cannot program it with '29LV800B' option.
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(in VisionClick flash programming tools)
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I don't know why...
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1.4. Save boot monitor program *IMPORTANT*
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Upload boot monitor program from board to file.
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boot monitor program starts at 0xFFF00000
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1.5. Test flash memory programming
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Try to erase boot program in the flash memory,
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and re-write them.
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*WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE
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BEFORE ERASING FLASH
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###############################################################
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# 2. U-Boot setting
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###############################################################
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2.1. Download U-Boot tarball at
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ftp://ftp.denx.de
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(The latest version is ppcboot-0.8.1.tar.bz2)
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To extract the archive use the following syntax :
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> bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf -
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2.2. Add the following lines in '.profile'
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export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin
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2.3. Make board specific config, for example:
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> cd ppcboot-0.8.1
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> make TQM860L_config
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Now we can build ppcboot bin files.
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After make all, you must see these files in your
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ppcboot root directory.
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ppcboot
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ppcboot.bin
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ppcboot.srec
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ppcboot.map
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2.4. Make your own board directory into the
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ppcboot-0.8.1/board
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and make your board-specific files here.
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For exmanple, tqm8xx files are composed of
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.depend : Nothing
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Makefile : To make config file
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config.mk : Sets base address
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flash.c : Flash memory control files
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ppcboot.lds : linker(ld) script? (I don't know this yet)
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tqm8xx.c : DRAM control and board check routines
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And, add your board config lines in the
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ppcboot-0.8.1/Makefile
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Finally, add config_(your board).h file in the
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ppcboot-0.8.1/include/
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I've made board/rpxlite directory, and just copied
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tqm8xx settings for now.
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Rebuild ppcboot for rpxlite board:
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> make rpxlite_config
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> make
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###############################################################
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# 3. U-Boot porting
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###############################################################
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3.1. My RPXlite files are based on tqm8xx board files.
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> cd board
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> cp -r tqm8xx RPXLITE
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> cd RPXLITE
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> mv tqm8xx.c RPXLITE.c
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> cd ../../include
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> cp config_tqm8xx.h config_RPXLITE.h
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3.2. Modified files are:
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board/RPXLITE/RPXLITE.c /* DRAM-related routines */
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board/RPXLITE/flash.c /* flash-related routines */
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board/RPXLITE/config.mk /* set text base address */
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arch/powerpc/cpu/mpc8xx/serial.c /* board specific register setting */
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include/config_RPXLITE.h /* board specific registers */
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See 'reg_config.txt' for register values in detail.
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###############################################################
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# 4. Running Linux
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###############################################################
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###############################################################
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# Misc Information
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###############################################################
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mem_config.txt:
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===============
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Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device
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manufacturer id : 01 (AMD)
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device id : 5B (AM29LV800B)
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size : 4Mbyte
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sector # : 19
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Sector information :
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number start addr. size
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00 FFC0_0000 64
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01 FFC1_0000 32
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02 FFC1_8000 32
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03 FFC2_0000 128
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04 FFC4_0000 256
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05 FFC8_0000 256
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06 FFCC_0000 256
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07 FFD0_0000 256
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08 FFD4_0000 256
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09 FFD8_0000 256
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10 FFDC_0000 256
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11 FFE0_0000 256
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12 FFE4_0000 256
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13 FFE8_0000 256
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14 FFEC_0000 256
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15 FFF0_0000 256
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16 FFF4_0000 256
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17 FFF8_0000 256
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18 FFFC_0000 256
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reg_config.txt:
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===============
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/*------------------------------------------------------------------- */
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/*------------------------------------------------------------------- */
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/* SIU (System Interface Unit) */
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/* */
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/*------------------------------------------------------------------- */
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/*------------------------------------------------------------------- */
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/*### IMMR */
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/*### Internal Memory Map Register */
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/*### Chap. 11.4.1 */
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ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */
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PARTNUM = 0x21
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MASKNUM = 0x00
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=> 0xFA20 2100
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---------------------------------------------------------------------
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/*### SIUMCR */
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/*### SIU Module Configuration Register */
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/*### Chap. 11.4.2 */
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/*### Offset : 0x0000 0000 */
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EARB = 0
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EARP = 0
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DSHW = 0
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DBGC = 0
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DBPC = 0
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FRC = 0
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DLK = 0
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OPAR = 0
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PNCS = 0
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DPC = 0
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MPRE = 0
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MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */
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AEME = 0
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SEME = 0
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BSC = 0
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GB5E = 0
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B2DD = 0
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B3DD = 0
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=> 0x0000 0800
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---------------------------------------------------------------------
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/*### SYPCR */
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/*### System Protection Control Register */
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/*### Chap. 11.4.3 */
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/*### Offset : 0x0000 0004 */
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SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */
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BMT = 0x06 /* BUS monitoring timing */
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BME = 1 /* BUS monitor enable */
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SWF = 1
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SWE = 0 /* SW watchdog disable */
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SWRI = 0
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SWP = 1
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=> 0xFFFF 0689
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---------------------------------------------------------------------
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/*### TESR */
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/*### Transfer Error Status Register */
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/*### Chap. 11.4.4 */
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/*### Offset : 0x0000 0020 */
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IEXT = 0
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ITMT = 0
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IPB = 0000
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DEXT = 0
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DTMT = 0
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DPB = 0000
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=> 0x0000 0000
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---------------------------------------------------------------------
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/*### SIPEND */
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/*### SIU Interrupt Pending Register */
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/*### Chap. 11.5.4.1 */
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/*### Offset : 0x0000 0010 */
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IRQ0~IRQ7 = 0
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LVL0~LVL7 = 0
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=> 0x0000 0000
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---------------------------------------------------------------------
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/*### SIMASK */
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/*### SIU Interrupt Mask Register */
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/*### Chap. 11.5.4.2 */
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/*### Offset : 0x0000 0014 */
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IRM0~IRM7 = 0 /* Mask all interrupts */
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LVL0~LVL7 = 0
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=> 0x0000 0000
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---------------------------------------------------------------------
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/*### SIEL */
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/*### SIU Interrupt Edge/Level Register */
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/*### Chap. 11.5.4.3 */
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/*### Offset : 0x0000 0018 */
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ED0~ED7 = 0 /* Low level triggered */
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WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */
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=> 0x0000 0000
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---------------------------------------------------------------------
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/*### SIVEC */
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/*### SIU Interrupt Vector Register */
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/*### Chap. 11.5.4.4 */
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/*### Offset : 0x0000 001C */
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INTC = 3C /* The lowest interrupt is pending..(?) */
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=> 0x3C00 0000
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---------------------------------------------------------------------
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/*### SWSR */
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/*### Software Service Register */
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/*### Chap. 11.7.1 */
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/*### Offset : 0x0000 001E */
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SEQ = 0
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=> 0x0000
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---------------------------------------------------------------------
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/*### SDCR */
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/*### SDMA Configuration Register */
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/*### Chap. 20.2.1 */
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/*### Offset : 0x0000 0032 */
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FRZ = 0
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RAID = 01 /* Priority level 5 (BR5) (normal operation) */
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=> 0x0000 0001
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/*------------------------------------------------------------------- */
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/*------------------------------------------------------------------- */
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/* UPMA (User Programmable Machine A) */
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/* */
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/*------------------------------------------------------------------- */
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/*------------------------------------------------------------------- */
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/*### Chap. 16.6.4.1 */
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/*### Offset = 0x0000 017c */
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T0 = CFFF CC24 /* Single Read */
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T1 = 0FFF CC04
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T2 = 0CAF CC04
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T3 = 03AF CC08
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T4 = 3FBF CC27 /* last */
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T5 = FFFF CC25
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T6 = FFFF CC25
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T7 = FFFF CC25
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T8 = CFFF CC24 /* Burst Read */
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T9 = 0FFF CC04
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T10 = 0CAF CC84
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T11 = 03AF CC88
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T12 = 3FBF CC27 /* last */
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T13 = FFFF CC25
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T14 = FFFF CC25
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T15 = FFFF CC25
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T16 = FFFF CC25
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T17 = FFFF CC25
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T18 = FFFF CC25
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T19 = FFFF CC25
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T20 = FFFF CC25
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T21 = FFFF CC25
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T22 = FFFF CC25
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T23 = FFFF CC25
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T24 = CFFF CC24 /* Single Write */
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T25 = 0FFF CC04
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T26 = 0CFF CC04
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T27 = 03FF CC00
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T28 = 3FFF CC27 /* last */
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T29 = FFFF CC25
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T30 = FFFF CC25
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T31 = FFFF CC25
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T32 = CFFF CC24 /* Burst Write */
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T33 = 0FFF CC04
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T34 = 0CFF CC80
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T35 = 03FF CC8C
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T36 = 0CFF CC00
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T37 = 33FF CC27 /* last */
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T38 = FFFF CC25
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T39 = FFFF CC25
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T40 = FFFF CC25
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T41 = FFFF CC25
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T42 = FFFF CC25
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T43 = FFFF CC25
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T44 = FFFF CC25
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T45 = FFFF CC25
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T46 = FFFF CC25
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T47 = FFFF CC25
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T48 = C0FF CC24 /* Refresh */
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T49 = 03FF CC24
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T50 = 0FFF CC24
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T51 = 0FFF CC24
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T52 = 3FFF CC27 /* last */
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T53 = FFFF CC25
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T54 = FFFF CC25
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T55 = FFFF CC25
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T56 = FFFF CC25
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T57 = FFFF CC25
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T58 = FFFF CC25
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T59 = FFFF CC25
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T60 = FFFF CC25 /* Exception */
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T61 = FFFF CC25
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T62 = FFFF CC25
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T63 = FFFF CC25
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/*------------------------------------------------------------------- */
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/*------------------------------------------------------------------- */
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/* UPMB */
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/* */
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/*------------------------------------------------------------------- */
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/*------------------------------------------------------------------- */
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---------------------------------------------------------------------
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/*### Chap. 16.6.4.1 */
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/*------------------------------------------------------------------- */
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/*------------------------------------------------------------------- */
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/* MEMC */
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/* */
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/*------------------------------------------------------------------- */
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/*------------------------------------------------------------------- */
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---------------------------------------------------------------------
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/*### BR0 & OR0 */
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/*### Base Registers & Option Registers */
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/*### Chap. 16.4.1 & 16.4.2 */
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/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */
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/*### Flash memory */
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BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */
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AT = 000
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PS = 00
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PARE = 0
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WP = 0
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MS = 0 /* GPCM */
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V = 1 /* Valid */
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=> 0xFE00 0001
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AM = 1111 1110 0000 0000 0 /* 32MBytes */
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ATM = 000
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CSNT/SAM = 0
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ACS/G5LA,G5LS = 00
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BIH = 1 /* Burst inhibited */
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SCY = 0100 /* cycle length = 4 */
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SETA = 0
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TRLX = 0
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EHTR = 0
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=> 0xFE00 0140
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/*### BR1 & OR1 */
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/*### Base Registers & Option Registers */
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/*### Chap. 16.4.1 & 16.4.2 */
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/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */
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/*### SDRAM */
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BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */
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AT = 000
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PS = 00
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PARE = 0
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WP = 0
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MS = 1 /* UPMA */
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V = 1 /* Valid */
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=> 0x0000 0081
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AM = 1111 1110 0000 0000 /* 32MBytes */
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ATM = 000
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CSNT/SAM = 1
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ACS/G5LA,G5LS = 11
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BIH = 0
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SCY = 0000 /* cycle length = 0 */
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SETA = 0
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TRLX = 0
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EHTR = 0
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=> 0xFE00 0E00
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/*### BR2 & OR2 */
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/*### Base Registers & Option Registers */
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/*### Chap. 16.4.1 & 16.4.2 */
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/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */
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BR2 & OR2 = 0x0000 0000 /* Not used */
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/*### BR3 & OR3 */
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/*### Base Registers & Option Registers */
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/*### Chap. 16.4.1 & 16.4.2 */
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/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */
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/*### BCSR */
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BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */
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AT = 000
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PS = 00
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PARE = 0
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WP = 0
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MS = 0 /* GPCM */
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V = 1 /* Valid */
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=> 0xFA40 0001
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AM = 1111 1111 0111 1111 1 /* (?) */
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ATM = 000
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CSNT/SAM = 1
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ACS/G5LA,G5LS = 00
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BIH = 1 /* Burst inhibited */
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SCY = 0001 /* cycle length = 1 */
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SETA = 0
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TRLX = 0
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=> 0xFF7F 8910
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/*### BR4 & OR4 */
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/*### Base Registers & Option Registers */
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/*### Chap. 16.4.1 & 16.4.2 */
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/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */
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/*### NVRAM & SRAM */
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BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */
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AT = 000
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PS = 01
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PARE = 0
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WP = 0
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MS = 0 /* GPCM */
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V = 1 /* Valid */
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=> 0xFA00 0401
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AM = 1111 1111 1111 1000 0 /* 8MByte */
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ATM = 000
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CSNT/SAM = 1
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ACS/G5LA,G5LS = 00
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BIH = 1 /* Burst inhibited */
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SCY = 0111 /* cycle length = 7 */
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SETA = 0
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TRLX = 0
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=> 0xFFF8 0970
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/*### BR5 & OR5 */
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/*### Base Registers & Option Registers */
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/*### Chap. 16.4.1 & 16.4.2 */
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/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */
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BR5 & OR5 = 0x0000 0000 /* Not used */
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/*### BR6 & OR6 */
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/*### Base Registers & Option Registers */
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/*### Chap. 16.4.1 & 16.4.2 */
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/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */
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BR6 & OR6 = 0x0000 0000 /* Not used */
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/*### BR7 & OR7 */
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/*### Base Registers & Option Registers */
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/*### Chap. 16.4.1 & 16.4.2 */
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/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */
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BR7 & OR7 = 0x0000 0000 /* Not used */
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/*### MAR */
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/*### Memory Address Register */
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/*### Chap. 16.4.7 */
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/*### Offset : 0x0000 0164 */
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MA = External memory address
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/*### MCR */
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/*### Memory Command Register */
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/*### Chap. 16.4.5 */
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/*### Offset : 0x0000 0168 */
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OP = xx /* Command op code */
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UM = 1 /* Select UPMA */
|
|
MB = 001 /* Select CS1 */
|
|
MCLF = xxxx /* Loop times */
|
|
MAD = xx xxxx /* Memory array index */
|
|
|
|
/*### MAMR */
|
|
/*### Machine A Mode Register */
|
|
/*### Chap. 16.4.4 */
|
|
/*### Offset : 0x0000 0170 */
|
|
|
|
PTA = 0101 1000
|
|
PTAE = 1 /* Periodic timer A enabled */
|
|
AMA = 010
|
|
DSA = 00
|
|
G0CLA = 000
|
|
GPLA4DIS = 1
|
|
RLFA = 0100
|
|
WLFA = 0011
|
|
TLFA = 0000
|
|
|
|
=> 0x58A0 1430
|
|
|
|
/*### MBMR */
|
|
/*### Machine B Mode Register */
|
|
/*### Chap. 16.4.4 */
|
|
/*### Offset : 0x0000 0174 */
|
|
|
|
PTA = 0100 1110
|
|
PTAE = 0 /* Periodic timer B disabled */
|
|
AMA = 000
|
|
DSA = 00
|
|
G0CLA = 000
|
|
GPLA4DIS = 1
|
|
RLFA = 0000
|
|
WLFA = 0000
|
|
TLFA = 0000
|
|
|
|
=> 0x4E00 1000
|
|
|
|
/*### MSTAT */
|
|
/*### Memory Status Register */
|
|
/*### Chap. 16.4.3 */
|
|
/*### Offset : 0x0000 0178 */
|
|
|
|
PER0~PER7 = Parity error
|
|
WPER = Write protection error
|
|
|
|
=> 0x0000
|
|
|
|
/*### MPTPR */
|
|
/*### Memory Periodic Timer Prescaler Register */
|
|
/*### Chap. 16.4.8 */
|
|
/*### Offset : 0x0000 017A */
|
|
|
|
PTP = 0000 1000 /* Divide by 8 */
|
|
|
|
=> 0x0800
|
|
|
|
/*### MDR */
|
|
/*### Memory Data Register */
|
|
/*### Chap. 16.4.6 */
|
|
/*### Offset : 0x0000 017C */
|
|
|
|
MD = Memory data contains the RAM array word
|
|
|
|
|
|
/*------------------------------------------------------------------- */
|
|
/*------------------------------------------------------------------- */
|
|
/* TIMERS */
|
|
/* */
|
|
/*------------------------------------------------------------------- */
|
|
/*------------------------------------------------------------------- */
|
|
---------------------------------------------------------------------
|
|
|
|
/*### TBREFx */
|
|
/*### Timebase Reference Registers */
|
|
/*### Chap. 11.9.2 */
|
|
/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */
|
|
/*### (Locked) */
|
|
|
|
TBREFF0 = 0xFFFF FFFF
|
|
TBREFF1 = 0xFFFF FFFF
|
|
|
|
---------------------------------------------------------------------
|
|
|
|
/*### TBSCR */
|
|
/*### Timebase Status and Control Registers */
|
|
/*### Chap. 11.9.3 */
|
|
/*### Offset : 0x0000 0200 */
|
|
/*### (Locked) */
|
|
|
|
TBIRQ = 00000000
|
|
REF0 = 0
|
|
REF1 = 0
|
|
REFE0 = 0 /* Reference interrupt disable */
|
|
REFE1 = 0
|
|
TBF = 1
|
|
TBE = 1 /* Timebase enable */
|
|
|
|
=> 0x0003
|
|
|
|
---------------------------------------------------------------------
|
|
|
|
/*### RTCSC */
|
|
/*### Real-Time Clock Status and Control Registers */
|
|
/*### Chap. 11.10.1 */
|
|
/*### Offset : 0x0000 0220 */
|
|
/*### (Locked) */
|
|
|
|
RTCIRQ = 00000000
|
|
SEC = 1
|
|
ALR = 0
|
|
38K = 0 /* PITRTCLK is driven by 32.768KHz */
|
|
SIE = 0
|
|
ALE = 0
|
|
RTF = 0
|
|
RTE = 1 /* Real-Time clock enabled */
|
|
|
|
=> 0x0081
|
|
|
|
---------------------------------------------------------------------
|
|
|
|
/*### RTC */
|
|
/*### Real-Time Clock Registers */
|
|
/*### Chap. 11.10.2 */
|
|
/*### Offset : 0x0000 0224 */
|
|
/*### (Locked) */
|
|
|
|
RTC = Real time clock measured in second
|
|
|
|
---------------------------------------------------------------------
|
|
|
|
/*### RTCAL */
|
|
/*### Real-Time Clock Alarm Registers */
|
|
/*### Chap. 11.10.3 */
|
|
/*### Offset : 0x0000 022C */
|
|
/*### (Locked) */
|
|
|
|
ALARM = 0xFFFF FFFF
|
|
|
|
---------------------------------------------------------------------
|
|
|
|
/*### RTSEC */
|
|
/*### Real-Time Clock Alarm Second Registers */
|
|
/*### Chap. 11.10.4 */
|
|
/*### Offset : 0x0000 0228 */
|
|
/*### (Locked) */
|
|
|
|
COUNTER = Counter bits(fraction of a second)
|
|
|
|
---------------------------------------------------------------------
|
|
|
|
/*### PISCR */
|
|
/*### Periodic Interrupt Status and Control Register */
|
|
/*### Chap. 11.11.1 */
|
|
/*### Offset : 0x0000 0240 */
|
|
/*### (Locked) */
|
|
|
|
PIRQ = 0
|
|
PS = 0 /* Write 1 to clear */
|
|
PIE = 0
|
|
PITF = 1
|
|
PTE = 0 /* PIT disabled */
|
|
|
|
---------------------------------------------------------------------
|
|
|
|
/*### PITC */
|
|
/*### PIT Count Register */
|
|
/*### Chap. 11.11.2 */
|
|
/*### Offset : 0x0000 0244 */
|
|
/*### (Locked) */
|
|
|
|
PITC = PIT count
|
|
|
|
---------------------------------------------------------------------
|
|
|
|
/*### PITR */
|
|
/*### PIT Register */
|
|
/*### Chap. 11.11.3 */
|
|
/*### Offset : 0x0000 0248 */
|
|
/*### (Locked) */
|
|
|
|
PIT = PIT count /* Read only */
|
|
|
|
|
|
/*------------------------------------------------------------------- */
|
|
/*------------------------------------------------------------------- */
|
|
/* CLOCKS */
|
|
/* */
|
|
/*------------------------------------------------------------------- */
|
|
/*------------------------------------------------------------------- */
|
|
---------------------------------------------------------------------
|
|
|
|
|
|
---------------------------------------------------------------------
|
|
|
|
/*### SCCR */
|
|
/*### System Clock and Reset Control Register */
|
|
/*### Chap. 15.6.1 */
|
|
/*### Offset : 0x0000 0280 */
|
|
/*### (Locked) */
|
|
|
|
COM = 11 /* Clock output disabled */
|
|
TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */
|
|
RTDIV = 0 /* The clock is divided by 4 */
|
|
RTSEL = 0 /* OSCM(Crystal oscillator) is selected */
|
|
CRQEN = 0
|
|
PRQEN = 0
|
|
EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */
|
|
DFSYNC = 00 /* Divided by 1 (normal operation) */
|
|
DFBRG = 00 /* Divided by 1 (normal operation) */
|
|
DFNL = 000
|
|
DFNH = 000
|
|
|
|
=> 0x6200 0000
|
|
|
|
---------------------------------------------------------------------
|
|
|
|
/*### PLPRCR */
|
|
/*### PLL, Low-Power, and Reset Control Register */
|
|
/*### Chap. 15.6.2 */
|
|
/*### Offset : 0x0000 0284 */
|
|
/*### (Locked) */
|
|
|
|
MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */
|
|
SPLSS = 0
|
|
TEXPS = 0
|
|
TMIST = 0
|
|
CSRC = 0 /* The general system clock is generated by the DFNH field */
|
|
LPM = 00 /* Normal high/normal low mode */
|
|
CSR = 0
|
|
LOLRE = 0
|
|
FIOPD = 0
|
|
|
|
=> 0x0050 0000
|
|
|
|
---------------------------------------------------------------------
|
|
|
|
/*### RSR */
|
|
/*### Reset Status Register */
|
|
/*### Chap. 12.2 */
|
|
/*### Offset : 0x0000 0288 */
|
|
/*### (Locked) */
|
|
|
|
EHRS = External hard reset
|
|
ESRS = External soft reset
|
|
LLRS = Loss-of-lock reset
|
|
SWRS = Software watchdog reset
|
|
CSRS = Check stop reset
|
|
DBHRS = Debug port hard reset
|
|
DBSRS = Debug port soft reset
|
|
JTRS = JTAG reset
|
|
|
|
|
|
/*------------------------------------------------------------------- */
|
|
/*------------------------------------------------------------------- */
|
|
/* DMA */
|
|
/* */
|
|
/*------------------------------------------------------------------- */
|
|
/*------------------------------------------------------------------- */
|
|
---------------------------------------------------------------------
|
|
|
|
/*### SDSR */
|
|
/*### SDMA Status Register */
|
|
/*### Chap. 20.2.2 */
|
|
/*### Offset : 0x0000 0908 */
|
|
|
|
SBER = 0 /* SDMA channel bus error */
|
|
DSP2 = 0 /* DSP chain2 (Tx) interrupt */
|
|
DSP1 = 0 /* DSP chain1 (Rx) interrupt */
|
|
|
|
=> 0x00
|
|
|
|
/*### SDMR */
|
|
/*### SDMA Mask Register */
|
|
/*### Chap. 20.2.3 */
|
|
/*### Offset : 0x0000 090C */
|
|
|
|
SBER = 0
|
|
DSP2 = 0
|
|
DSP1 = 0 /* All interrupts are masked */
|
|
|
|
=> 0x00
|
|
|
|
/*### SDAR */
|
|
/*### SDMA Address Register */
|
|
/*### Chap. 20.2.4 */
|
|
/*### Offset : 0x0000 0904 */
|
|
|
|
AR = 0xxxxx xxxx /* current system address */
|
|
|
|
=> 0xFA20 23AC
|
|
|
|
/*### IDSRx */
|
|
/*### IDMA Status Register */
|
|
/*### Chap. 20.3.3.2 */
|
|
/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */
|
|
|
|
AD = 0
|
|
DONE = 0
|
|
OB = 0
|
|
|
|
=> 0x00
|
|
|
|
/*### IDMRx */
|
|
/*### IDMA Mask Register */
|
|
/*### Chap. 20.3.3.3 */
|
|
/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */
|
|
|
|
AD = 0
|
|
DONE = 0
|
|
OB = 0
|