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6d82517836
Now that new SPI NOR layer uses stateless 4 byte opcodes by default, don't enable SPI_FLASH_BAR. For SPI controllers that cannot support 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to not break functionality. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
61 lines
1.3 KiB
Plaintext
61 lines
1.3 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_MX6=y
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CONFIG_SYS_TEXT_BASE=0x87800000
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CONFIG_TARGET_MX6SXSABREAUTO=y
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# CONFIG_CMD_BMODE is not set
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg"
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CONFIG_SUPPORT_RAW_INITRD=y
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CONFIG_BOUNCE_BUFFER=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_NAND_TRIMFFS=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
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CONFIG_DM_GPIO=y
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CONFIG_DM_PCA953X=y
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CONFIG_DM_I2C=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_NAND=y
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CONFIG_NAND_MXS=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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CONFIG_DM_PMIC=y
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CONFIG_DM_PMIC_PFUZE100=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_PFUZE100=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_FSL_QSPI=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_ASIX=y
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