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6787c1ece0
Adding the support for 2 boards sharing common code for Ocelot chip: PCB120 and PCB123 Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
83 lines
2.7 KiB
C
83 lines
2.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#ifndef __VCOREIII_H
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#define __VCOREIII_H
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#include <linux/sizes.h>
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/* Onboard devices */
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#define CONFIG_SYS_MALLOC_LEN 0x100000
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#define CONFIG_SYS_LOAD_ADDR 0x00100000
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#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
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#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
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#ifdef CONFIG_SOC_LUTON
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#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333
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#else
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#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
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#endif
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#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
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#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_OFFSET (1024 * 1024)
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#define CONFIG_ENV_SIZE (256 * 1024)
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#define CONFIG_ENV_SECT_SIZE (256 * 1024)
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SPI_MAX_HZ 0 /* This force to read from DT */
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#define CONFIG_ENV_SPI_MODE 0 /* This force to read from DT */
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#endif
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
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#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
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#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
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#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M)
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#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
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#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M)
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#else
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#error Unknown DDR size - please add!
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#endif
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_BOARD_EARLY_INIT_R
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#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
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#define VCOREIII_DEFAULT_MTD_ENV \
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"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
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"mtdids="CONFIG_MTDIDS_DEFAULT"\0"
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#else
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#define VCOREIII_DEFAULT_MTD_ENV /* Go away */
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#endif
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#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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VCOREIII_DEFAULT_MTD_ENV \
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"loadaddr=0x81000000\0" \
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"spi_image_off=0x00100000\0" \
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"console=ttyS0,115200\0" \
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"setup=setenv bootargs console=${console} ${mtdparts}" \
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"${bootargs_extra}\0" \
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"spiboot=run setup; sf probe; sf read ${loadaddr}" \
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"${spi_image_off} 0x600000; bootm ${loadaddr}\0" \
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"ubootfile=u-boot.bin\0" \
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"update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};" \
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"sf erase UBoot 0x100000;" \
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"sf write ${loadaddr} UBoot ${filesize}\0" \
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"bootcmd=run spiboot\0" \
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""
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#endif /* __VCOREIII_H */
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