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88 lines
1.8 KiB
C
88 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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*
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/system_manager.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/agilex-clock.h>
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DECLARE_GLOBAL_DATA_PTR;
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static ulong cm_get_rate_dm(u32 id)
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{
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struct udevice *dev;
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struct clk clk;
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ulong rate;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(socfpga_agilex_clk),
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&dev);
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if (ret)
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return 0;
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clk.id = id;
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ret = clk_request(dev, &clk);
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if (ret < 0)
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return 0;
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rate = clk_get_rate(&clk);
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clk_free(&clk);
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if ((rate == (unsigned long)-ENOSYS) ||
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(rate == (unsigned long)-ENXIO) ||
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(rate == (unsigned long)-EIO)) {
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debug("%s id %u: clk_get_rate err: %ld\n",
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__func__, id, rate);
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return 0;
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}
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return rate;
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}
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static u32 cm_get_rate_dm_khz(u32 id)
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{
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return cm_get_rate_dm(id) / 1000;
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}
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unsigned long cm_get_mpu_clk_hz(void)
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{
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return cm_get_rate_dm(AGILEX_MPU_CLK);
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}
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unsigned int cm_get_l4_sys_free_clk_hz(void)
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{
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return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
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}
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u32 cm_get_qspi_controller_clk_hz(void)
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{
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return readl(socfpga_get_sysmgr_addr() +
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SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
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}
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void cm_print_clock_quick_summary(void)
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{
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printf("MPU %10d kHz\n",
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cm_get_rate_dm_khz(AGILEX_MPU_CLK));
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printf("L4 Main %8d kHz\n",
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cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
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printf("L4 sys free %8d kHz\n",
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cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
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printf("L4 MP %8d kHz\n",
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cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
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printf("L4 SP %8d kHz\n",
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cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
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printf("SDMMC %8d kHz\n",
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cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
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}
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