mirror of
https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
374 lines
11 KiB
C
374 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Meson G12A USB2 PHY driver
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*
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* Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstron@baylibre.com>
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*/
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#include <common.h>
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#include <log.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <bitfield.h>
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#include <dm.h>
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#include <errno.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <linux/delay.h>
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#include <linux/printk.h>
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#include <power/regulator.h>
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#include <power-domain.h>
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#include <reset.h>
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#include <clk.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <linux/bitfield.h>
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#define PHY_CTRL_R0 0x0
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#define PHY_CTRL_R1 0x4
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#define PHY_CTRL_R2 0x8
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#define PHY_CTRL_R3 0xc
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#define PHY_CTRL_R3_SQUELCH_REF GENMASK(1, 0)
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#define PHY_CTRL_R3_HSDIC_REF GENMASK(3, 2)
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#define PHY_CTRL_R3_DISC_THRESH GENMASK(7, 4)
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#define PHY_CTRL_R4 0x10
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#define PHY_CTRL_R4_CALIB_CODE_7_0 GENMASK(7, 0)
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#define PHY_CTRL_R4_CALIB_CODE_15_8 GENMASK(15, 8)
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#define PHY_CTRL_R4_CALIB_CODE_23_16 GENMASK(23, 16)
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#define PHY_CTRL_R4_I_C2L_CAL_EN BIT(24)
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#define PHY_CTRL_R4_I_C2L_CAL_RESET_N BIT(25)
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#define PHY_CTRL_R4_I_C2L_CAL_DONE BIT(26)
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#define PHY_CTRL_R4_TEST_BYPASS_MODE_EN BIT(27)
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#define PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0 GENMASK(29, 28)
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#define PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2 GENMASK(31, 30)
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#define PHY_CTRL_R5 0x14
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#define PHY_CTRL_R6 0x18
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#define PHY_CTRL_R7 0x1c
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#define PHY_CTRL_R8 0x20
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#define PHY_CTRL_R9 0x24
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#define PHY_CTRL_R10 0x28
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#define PHY_CTRL_R11 0x2c
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#define PHY_CTRL_R12 0x30
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#define PHY_CTRL_R13 0x34
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#define PHY_CTRL_R13_CUSTOM_PATTERN_19 GENMASK(7, 0)
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#define PHY_CTRL_R13_LOAD_STAT BIT(14)
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#define PHY_CTRL_R13_UPDATE_PMA_SIGNALS BIT(15)
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#define PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET GENMASK(20, 16)
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#define PHY_CTRL_R13_CLEAR_HOLD_HS_DISCONNECT BIT(21)
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#define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_VAL BIT(22)
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#define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_EN BIT(23)
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#define PHY_CTRL_R13_I_C2L_HS_EN BIT(24)
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#define PHY_CTRL_R13_I_C2L_FS_EN BIT(25)
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#define PHY_CTRL_R13_I_C2L_LS_EN BIT(26)
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#define PHY_CTRL_R13_I_C2L_HS_OE BIT(27)
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#define PHY_CTRL_R13_I_C2L_FS_OE BIT(28)
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#define PHY_CTRL_R13_I_C2L_HS_RX_EN BIT(29)
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#define PHY_CTRL_R13_I_C2L_FSLS_RX_EN BIT(30)
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#define PHY_CTRL_R14 0x38
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#define PHY_CTRL_R15 0x3c
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#define PHY_CTRL_R16 0x40
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#define PHY_CTRL_R16_MPLL_M GENMASK(8, 0)
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#define PHY_CTRL_R16_MPLL_N GENMASK(14, 10)
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#define PHY_CTRL_R16_MPLL_TDC_MODE BIT(20)
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#define PHY_CTRL_R16_MPLL_SDM_EN BIT(21)
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#define PHY_CTRL_R16_MPLL_LOAD BIT(22)
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#define PHY_CTRL_R16_MPLL_DCO_SDM_EN BIT(23)
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#define PHY_CTRL_R16_MPLL_LOCK_LONG GENMASK(25, 24)
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#define PHY_CTRL_R16_MPLL_LOCK_F BIT(26)
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#define PHY_CTRL_R16_MPLL_FAST_LOCK BIT(27)
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#define PHY_CTRL_R16_MPLL_EN BIT(28)
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#define PHY_CTRL_R16_MPLL_RESET BIT(29)
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#define PHY_CTRL_R16_MPLL_LOCK BIT(30)
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#define PHY_CTRL_R16_MPLL_LOCK_DIG BIT(31)
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#define PHY_CTRL_R17 0x44
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#define PHY_CTRL_R17_MPLL_FRAC_IN GENMASK(13, 0)
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#define PHY_CTRL_R17_MPLL_FIX_EN BIT(16)
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#define PHY_CTRL_R17_MPLL_LAMBDA1 GENMASK(19, 17)
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#define PHY_CTRL_R17_MPLL_LAMBDA0 GENMASK(22, 20)
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#define PHY_CTRL_R17_MPLL_FILTER_MODE BIT(23)
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#define PHY_CTRL_R17_MPLL_FILTER_PVT2 GENMASK(27, 24)
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#define PHY_CTRL_R17_MPLL_FILTER_PVT1 GENMASK(31, 28)
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#define PHY_CTRL_R18 0x48
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#define PHY_CTRL_R18_MPLL_LKW_SEL GENMASK(1, 0)
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#define PHY_CTRL_R18_MPLL_LK_W GENMASK(5, 2)
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#define PHY_CTRL_R18_MPLL_LK_S GENMASK(11, 6)
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#define PHY_CTRL_R18_MPLL_DCO_M_EN BIT(12)
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#define PHY_CTRL_R18_MPLL_DCO_CLK_SEL BIT(13)
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#define PHY_CTRL_R18_MPLL_PFD_GAIN GENMASK(15, 14)
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#define PHY_CTRL_R18_MPLL_ROU GENMASK(18, 16)
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#define PHY_CTRL_R18_MPLL_DATA_SEL GENMASK(21, 19)
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#define PHY_CTRL_R18_MPLL_BIAS_ADJ GENMASK(23, 22)
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#define PHY_CTRL_R18_MPLL_BB_MODE GENMASK(25, 24)
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#define PHY_CTRL_R18_MPLL_ALPHA GENMASK(28, 26)
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#define PHY_CTRL_R18_MPLL_ADJ_LDO GENMASK(30, 29)
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#define PHY_CTRL_R18_MPLL_ACG_RANGE BIT(31)
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#define PHY_CTRL_R19 0x4c
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#define PHY_CTRL_R20 0x50
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#define PHY_CTRL_R20_USB2_IDDET_EN BIT(0)
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#define PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0 GENMASK(3, 1)
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#define PHY_CTRL_R20_USB2_OTG_VBUSDET_EN BIT(4)
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#define PHY_CTRL_R20_USB2_AMON_EN BIT(5)
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#define PHY_CTRL_R20_USB2_CAL_CODE_R5 BIT(6)
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#define PHY_CTRL_R20_BYPASS_OTG_DET BIT(7)
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#define PHY_CTRL_R20_USB2_DMON_EN BIT(8)
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#define PHY_CTRL_R20_USB2_DMON_SEL_3_0 GENMASK(12, 9)
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#define PHY_CTRL_R20_USB2_EDGE_DRV_EN BIT(13)
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#define PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0 GENMASK(15, 14)
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#define PHY_CTRL_R20_USB2_BGR_ADJ_4_0 GENMASK(20, 16)
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#define PHY_CTRL_R20_USB2_BGR_START BIT(21)
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#define PHY_CTRL_R20_USB2_BGR_VREF_4_0 GENMASK(28, 24)
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#define PHY_CTRL_R20_USB2_BGR_DBG_1_0 GENMASK(30, 29)
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#define PHY_CTRL_R20_BYPASS_CAL_DONE_R5 BIT(31)
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#define PHY_CTRL_R21 0x54
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#define PHY_CTRL_R21_USB2_BGR_FORCE BIT(0)
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#define PHY_CTRL_R21_USB2_CAL_ACK_EN BIT(1)
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#define PHY_CTRL_R21_USB2_OTG_ACA_EN BIT(2)
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#define PHY_CTRL_R21_USB2_TX_STRG_PD BIT(3)
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#define PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0 GENMASK(5, 4)
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#define PHY_CTRL_R21_BYPASS_UTMI_CNTR GENMASK(15, 6)
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#define PHY_CTRL_R21_BYPASS_UTMI_REG GENMASK(25, 20)
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#define PHY_CTRL_R22 0x58
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#define PHY_CTRL_R23 0x5c
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#define RESET_COMPLETE_TIME 1000
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#define PLL_RESET_COMPLETE_TIME 100
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enum meson_soc_id {
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MESON_SOC_A1,
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MESON_SOC_G12A,
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};
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struct phy_meson_g12a_usb2_priv {
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struct regmap *regmap;
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#if CONFIG_IS_ENABLED(CLK)
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struct clk clk;
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#endif
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struct reset_ctl reset;
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#if CONFIG_IS_ENABLED(POWER_DOMAIN)
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struct power_domain pwrdm;
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#endif
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int soc_id;
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};
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static int phy_meson_g12a_usb2_init(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
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u32 value;
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int ret;
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_enable(&priv->clk);
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if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
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pr_err("failed to enable PHY clock\n");
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return ret;
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}
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#endif
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ret = reset_assert(&priv->reset);
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udelay(1);
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ret |= reset_deassert(&priv->reset);
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if (ret)
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return ret;
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udelay(RESET_COMPLETE_TIME);
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/* usb2_otg_aca_en == 0 */
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regmap_update_bits(priv->regmap, PHY_CTRL_R21, BIT(2), 0);
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/* PLL Setup : 24MHz * 20 / 1 = 480MHz */
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regmap_write(priv->regmap, PHY_CTRL_R16,
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FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) |
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FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) |
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PHY_CTRL_R16_MPLL_LOAD |
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FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) |
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PHY_CTRL_R16_MPLL_FAST_LOCK |
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PHY_CTRL_R16_MPLL_EN |
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PHY_CTRL_R16_MPLL_RESET);
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regmap_write(priv->regmap, PHY_CTRL_R17,
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FIELD_PREP(PHY_CTRL_R17_MPLL_FRAC_IN, 0) |
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FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA1, 7) |
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FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA0, 7) |
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FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) |
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FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9));
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value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
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FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
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FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
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FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
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FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
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FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
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FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
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FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
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FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
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FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
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PHY_CTRL_R18_MPLL_ACG_RANGE;
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if (priv->soc_id == MESON_SOC_A1)
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value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
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regmap_write(priv->regmap, PHY_CTRL_R18, value);
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udelay(PLL_RESET_COMPLETE_TIME);
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/* UnReset PLL */
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regmap_write(priv->regmap, PHY_CTRL_R16,
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FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) |
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FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) |
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PHY_CTRL_R16_MPLL_LOAD |
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FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) |
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PHY_CTRL_R16_MPLL_FAST_LOCK |
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PHY_CTRL_R16_MPLL_EN);
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/* PHY Tuning */
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regmap_write(priv->regmap, PHY_CTRL_R20,
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FIELD_PREP(PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0, 4) |
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PHY_CTRL_R20_USB2_OTG_VBUSDET_EN |
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FIELD_PREP(PHY_CTRL_R20_USB2_DMON_SEL_3_0, 15) |
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PHY_CTRL_R20_USB2_EDGE_DRV_EN |
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FIELD_PREP(PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0, 3) |
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FIELD_PREP(PHY_CTRL_R20_USB2_BGR_ADJ_4_0, 0) |
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FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) |
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FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0));
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if (priv->soc_id == MESON_SOC_G12A)
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regmap_write(priv->regmap, PHY_CTRL_R4,
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FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
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FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
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FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
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PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
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FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
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FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
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else if (priv->soc_id == MESON_SOC_A1)
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regmap_write(priv->regmap, PHY_CTRL_R21,
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PHY_CTRL_R21_USB2_CAL_ACK_EN |
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PHY_CTRL_R21_USB2_TX_STRG_PD |
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FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2));
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/* Tuning Disconnect Threshold */
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regmap_write(priv->regmap, PHY_CTRL_R3,
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FIELD_PREP(PHY_CTRL_R3_SQUELCH_REF, 0) |
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FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) |
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FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3));
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/* Analog Settings */
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if (priv->soc_id == MESON_SOC_G12A) {
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regmap_write(priv->regmap, PHY_CTRL_R14, 0);
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regmap_write(priv->regmap, PHY_CTRL_R13,
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PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
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FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
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} else if (priv->soc_id == MESON_SOC_A1) {
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regmap_write(priv->regmap, PHY_CTRL_R13,
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FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
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}
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return 0;
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}
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static int phy_meson_g12a_usb2_exit(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
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int ret;
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#if CONFIG_IS_ENABLED(CLK)
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clk_disable(&priv->clk);
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#endif
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ret = reset_assert(&priv->reset);
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if (ret)
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return ret;
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return 0;
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}
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struct phy_ops meson_g12a_usb2_phy_ops = {
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.init = phy_meson_g12a_usb2_init,
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.exit = phy_meson_g12a_usb2_exit,
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};
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int meson_g12a_usb2_phy_probe(struct udevice *dev)
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{
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struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
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int ret;
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priv->soc_id = (enum meson_soc_id)dev_get_driver_data(dev);
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ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
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if (ret)
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return ret;
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ret = reset_get_by_index(dev, 0, &priv->reset);
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if (ret == -ENOTSUPP)
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return 0;
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else if (ret)
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return ret;
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ret = reset_deassert(&priv->reset);
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if (ret) {
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reset_release_all(&priv->reset, 1);
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return ret;
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}
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#if CONFIG_IS_ENABLED(POWER_DOMAIN)
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ret = power_domain_get(dev, &priv->pwrdm);
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if (ret < 0 && ret != -ENODEV && ret != -ENOENT) {
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pr_err("failed to get power domain : %d\n", ret);
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return ret;
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}
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if (ret != -ENODEV && ret != -ENOENT) {
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ret = power_domain_on(&priv->pwrdm);
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if (ret < 0) {
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pr_err("failed to enable power domain\n");
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return ret;
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}
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}
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#endif
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0)
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return ret;
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#endif
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return 0;
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}
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static const struct udevice_id meson_g12a_usb2_phy_ids[] = {
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{
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.compatible = "amlogic,g12a-usb2-phy",
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.data = (ulong)MESON_SOC_G12A,
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},
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{
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.compatible = "amlogic,a1-usb2-phy",
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.data = (ulong)MESON_SOC_A1,
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},
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{ }
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};
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U_BOOT_DRIVER(meson_g12a_usb2_phy) = {
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.name = "meson_g12a_usb2_phy",
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.id = UCLASS_PHY,
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.of_match = meson_g12a_usb2_phy_ids,
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.probe = meson_g12a_usb2_phy_probe,
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.ops = &meson_g12a_usb2_phy_ops,
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.priv_auto = sizeof(struct phy_meson_g12a_usb2_priv),
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};
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