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cd2f6b8b95
Enable ROCKCHIP_SPL_BACK_TO_BROM and disable CONFIG_SPL_MMC_SUPPORT to save memory in order to enable add source code for dram capacity auto-detect. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
67 lines
1.6 KiB
Plaintext
67 lines
1.6 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_ROCKCHIP_RK3288=y
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CONFIG_TARGET_FENNEC_RK3288=y
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
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CONFIG_SILENT_CONSOLE=y
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CONFIG_CONSOLE_MUX=y
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_IMLS is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_GPIO=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_PMIC=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_REGMAP=y
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CONFIG_SPL_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_SPL_SYSCON=y
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# CONFIG_SPL_SIMPLE_BUS is not set
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CONFIG_CLK=y
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CONFIG_SPL_CLK=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_ROCKCHIP_DWMMC=y
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CONFIG_PINCTRL=y
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# CONFIG_PINCTRL_FULL is not set
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CONFIG_SPL_PINCTRL=y
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# CONFIG_SPL_PINCTRL_FULL is not set
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CONFIG_ROCKCHIP_RK3288_PINCTRL=y
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CONFIG_DM_PMIC=y
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CONFIG_PMIC_RK808=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_REGULATOR_RK808=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_RAM=y
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CONFIG_SPL_RAM=y
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART_BASE=0xff690000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550=y
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CONFIG_SYSRESET=y
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CONFIG_USE_TINY_PRINTF=y
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CONFIG_CMD_DHRYSTONE=y
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CONFIG_ERRNO_STR=y
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CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
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