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7ae8350f67
Currently in some cases SDRAM init requires global_data to be available and soon this will not be available prior to board_init_f(). Adjust the code paths in these cases to be correct. In some cases we had the SPL stack be in DDR as we might have large stacks (due to Falcon Mode + Environment). In these cases switch to CONFIG_SPL_STACK_R. In other cases we had simply been setting CONFIG_SPL_STACK into SRAM. In these cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also in SRAM) so drop those lines. Signed-off-by: Simon Glass <sjg@chromium.org> Tested on Beagleboard, Beagleboard xM Tested-by: Matt Porter <mporter@konsulko.com> Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard Tested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
252 lines
7.2 KiB
C
252 lines
7.2 KiB
C
/*
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* (C) Copyright 2006-2008
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* (C) Copyright 2009
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* Frederik Kriewitz <frederik@kriewitz.eu>
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*
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* Configuration settings for the DevKit8000 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
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#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
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/*
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* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
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* 64 bytes before this address should be set aside for u-boot.img's
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* header. That is 0x800FFFC0--0x80100000 should not be used for any
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* other needs.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80100000
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#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
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#define CONFIG_NAND
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#include <configs/ti_omap3_common.h>
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/* Display CPU and Board information */
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#define CONFIG_DISPLAY_CPUINFO 1
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#define CONFIG_DISPLAY_BOARDINFO 1
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#define CONFIG_MISC_INIT_R
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#define CONFIG_REVISION_TAG 1
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/* Size of malloc() pool */
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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/* Sector */
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#undef CONFIG_SYS_MALLOC_LEN
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
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/* Hardware drivers */
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/* DM9000 */
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_DRIVER_DM9000 1
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#define CONFIG_DM9000_BASE 0x2c000000
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#define DM9000_IO CONFIG_DM9000_BASE
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#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
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#define CONFIG_DM9000_USE_16BIT 1
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#define CONFIG_DM9000_NO_SROM 1
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#undef CONFIG_DM9000_DEBUG
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/* SPI */
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#undef CONFIG_SPI
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#undef CONFIG_OMAP3_SPI
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/* I2C */
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#undef CONFIG_SYS_I2C_OMAP24XX
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#define CONFIG_SYS_I2C_OMAP34XX
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/* TWL4030 */
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#define CONFIG_TWL4030_LED 1
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/* Board NAND Info */
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#define MTDIDS_DEFAULT "nand0=nand"
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#define MTDPARTS_DEFAULT "mtdparts=nand:" \
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"512k(x-loader)," \
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"1920k(u-boot)," \
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"128k(u-boot-env)," \
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"4m(kernel)," \
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"-(fs)"
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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#define CONFIG_JFFS2_NAND
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/* nand device jffs2 lives on */
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#define CONFIG_JFFS2_DEV "nand0"
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/* start of jffs2 partition */
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#define CONFIG_JFFS2_PART_OFFSET 0x680000
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#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
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/* partition */
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/* commands to include */
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#define CONFIG_CMD_DHCP /* DHCP support */
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#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
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#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
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#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
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#undef CONFIG_CMD_IMI /* iminfo */
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#undef CONFIG_CMD_SPI
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#undef CONFIG_CMD_GPIO
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#undef CONFIG_CMD_ASKENV
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#undef CONFIG_CMD_BOOTZ
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#undef CONFIG_SUPPORT_RAW_INITRD
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#undef CONFIG_FAT_WRITE
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#undef CONFIG_CMD_EXT4
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#undef CONFIG_CMD_FS_GENERIC
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/* BOOTP/DHCP options */
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_NISDOMAIN
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_BOOTP_NTPSERVER
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#define CONFIG_BOOTP_TIMEOFFSET
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#undef CONFIG_BOOTP_VENDOREX
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/* Environment information */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x82000000\0" \
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"console=ttyO2,115200n8\0" \
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"mmcdev=0\0" \
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"vram=12M\0" \
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"dvimode=1024x768MR-16@60\0" \
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"defaultdisplay=dvi\0" \
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"nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
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"kernelopts=rw\0" \
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"commonargs=" \
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"setenv bootargs console=${console} " \
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"vram=${vram} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapdss.def_disp=${defaultdisplay}\0" \
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"mmcargs=" \
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"run commonargs; " \
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"setenv bootargs ${bootargs} " \
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"root=/dev/mmcblk0p2 " \
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"rootwait " \
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"${kernelopts}\0" \
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"nandargs=" \
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"run commonargs; " \
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"setenv bootargs ${bootargs} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapdss.def_disp=${defaultdisplay} " \
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"root=/dev/mtdblock4 " \
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"rootfstype=jffs2 " \
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"${kernelopts}\0" \
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"netargs=" \
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"run commonargs; " \
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"setenv bootargs ${bootargs} " \
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"root=/dev/nfs " \
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"nfsroot=${serverip}:${rootpath},${nfsopts} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
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"${kernelopts} " \
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"dnsip1=${dnsip} " \
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"dnsip2=${dnsip2}\0" \
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"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source ${loadaddr}\0" \
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"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
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"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"nandboot=echo Booting from nand ...; " \
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"run nandargs; " \
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"nand read ${loadaddr} 280000 400000; " \
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"bootm ${loadaddr}\0" \
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"netboot=echo Booting from network ...; " \
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"dhcp ${loadaddr}; " \
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"run netargs; " \
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"bootm ${loadaddr}\0" \
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"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run nandboot; " \
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"fi; " \
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"fi; " \
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"else run nandboot; fi\0"
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#define CONFIG_BOOTCOMMAND "run autoboot"
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
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0x01000000) /* 16MB */
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/* NAND and environment organization */
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#define CONFIG_ENV_IS_IN_NAND 1
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#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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/* SRAM config */
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#define CONFIG_SYS_SRAM_START 0x40200000
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#define CONFIG_SYS_SRAM_SIZE 0x10000
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/* Defines for SPL */
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#undef CONFIG_SPL_MTD_SUPPORT
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#undef CONFIG_SPL_TEXT_BASE
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#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
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/* NAND boot config */
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#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
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/* SPL OS boot options */
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
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#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
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0x400000)
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
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#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
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#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
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#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
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#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
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#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
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#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
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#undef CONFIG_SYS_SPL_ARGS_ADDR
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#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
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#endif /* __CONFIG_H */
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