mirror of
https://github.com/u-boot/u-boot.git
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174 lines
4.4 KiB
C
174 lines
4.4 KiB
C
/*
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* U-boot - Configuration file for BF609 EZ-Kit board
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*/
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#ifndef __CONFIG_BF609_EZKIT_H__
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#define __CONFIG_BF609_EZKIT_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf609-0.0
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
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/* For ez-board version 1.0, else undef this */
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#define CONFIG_BFIN_BOARD_VERSION_1_0
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV
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* SCLK0 = SCLK / SCLK0_DIV
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* SCLK1 = SCLK / SCLK1_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ (25000000)
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF (0)
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-127 (where 0 means 128) */
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#define CONFIG_VCO_MULT (20)
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/* CCLK_DIV controls the core clock divider */
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/* Values can range from 0-31 (where 0 means 32) */
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#define CONFIG_CCLK_DIV (1)
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 0-31 (where 0 means 32) */
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#define CONFIG_SCLK_DIV (4)
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/* Values can range from 0-7 (where 0 means 8) */
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#define CONFIG_SCLK0_DIV (1)
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#define CONFIG_SCLK1_DIV (1)
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/* DCLK_DIV controls the DDR clock divider */
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/* Values can range from 0-31 (where 0 means 32) */
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#define CONFIG_DCLK_DIV (2)
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/* OCLK_DIV controls the output clock divider */
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/* Values can range from 0-127 (where 0 means 128) */
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#define CONFIG_OCLK_DIV (16)
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_SIZE 128
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#define CONFIG_SMC_GCTL_VAL 0x00000010
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#define CONFIG_SMC_B0CTL_VAL 0x01007011
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#define CONFIG_SMC_B0TIM_VAL 0x08170977
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#define CONFIG_SMC_B0ETIM_VAL 0x00092231
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
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#define CONFIG_HW_WATCHDOG
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/*
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* Network Settings
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*/
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#define ADI_CMDS_NETWORK
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#define CONFIG_NETCONSOLE
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#define CONFIG_NET_MULTI
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#define CONFIG_HOSTNAME "bf609-ezkit"
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#define CONFIG_DESIGNWARE_ETH
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#define CONFIG_PHY_ADDR 1
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#define CONFIG_DW_PORTS 1
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#define CONFIG_DW_ALTDESCRIPTOR
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_MII
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#define CONFIG_PHYLIB
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/* i2c Settings */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_ADI
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/*
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* Flash Settings
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*/
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_JFFS2
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#define CONFIG_SYS_FLASH_CFI_WIDTH 2
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0xb0000000
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 131
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#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
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/*
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* SPI Settings
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*/
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#define CONFIG_BFIN_SPI6XX
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#define CONFIG_ENV_SPI_MAX_HZ 25000000
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#define CONFIG_SF_DEFAULT_SPEED 25000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_ALL
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/*
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* Env Storage Settings
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*/
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x10000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
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#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET 0x60000
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#define CONFIG_ENV_SIZE 0x20000
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_OFFSET 0x8000
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#define CONFIG_ENV_SIZE 0x8000
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#define CONFIG_ENV_SECT_SIZE 0x8000
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#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
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#endif
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#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0xB0100000\0"
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/*
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* SDH Settings
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*/
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#define CONFIG_GENERIC_MMC
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#define CONFIG_MMC
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#define CONFIG_BFIN_SDH
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/*
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* Misc Settings
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*/
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_UART_CONSOLE 0
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_SOFTSWITCH
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#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4)
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#define CONFIG_BFIN_SOFT_SWITCH
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#define CONFIG_ADI_GPIO2
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#if 0
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#define CONFIG_UART_MEM 1024
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#undef CONFIG_UART_CONSOLE
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#undef CONFIG_JTAG_CONSOLE
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#undef CONFIG_UART_CONSOLE_IS_JTAG
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#endif
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#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024))
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/*
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* Run core 1 from L1 SRAM start address when init uboot on core 0
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*/
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/* #define CONFIG_CORE1_RUN 1 */
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/*
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* Pull in common ADI header for remaining command/environment setup
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*/
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#include <configs/bfin_adi_common.h>
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#endif
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