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c70564e6b1
u-boot/nand_spl
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Dave Liu c70564e6b1 NAND: Fix cache and memory inconsistency issue 
We load the secondary stage u-boot image from NAND to
system memory by nand_load, but we did not flush d-cache
to memory, nor invalidate i-cache before we jump to RAM.
When the system has cache enabled and the TLB/page attribute
of system memory is cacheable, it will cause issues.

- 83xx family is using the d-cache lock, so all of d-cache
  access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial
  cache lock. you will see the issue.

This patch fixes the cache issue.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-23 10:32:50 -06:00
..
board NAND: Fix cache and memory inconsistency issue 2009-01-23 10:32:50 -06:00
nand_boot_fsl_elbc.c NAND: Fix cache and memory inconsistency issue 2009-01-23 10:32:50 -06:00
nand_boot.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00