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d9506a6fdd
This patch adds ethernet gmac node for MT7623 with MT7530 gigabit switch. Signed-off-by: Mark Lee <Mark-MC.Lee@mediatek.com>
275 lines
6.7 KiB
Plaintext
275 lines
6.7 KiB
Plaintext
/*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*
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* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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*/
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#include <dt-bindings/clock/mt7623-clk.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/mt7623-power.h>
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#include <dt-bindings/reset/mtk-reset.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "mediatek,mt7623";
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interrupt-parent = <&sysirq>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt6589-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clocks = <&infracfg CLK_INFRA_CPUSEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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clock-frequency = <1300000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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clocks = <&infracfg CLK_INFRA_CPUSEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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clock-frequency = <1300000000>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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clocks = <&infracfg CLK_INFRA_CPUSEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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clock-frequency = <1300000000>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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clocks = <&infracfg CLK_INFRA_CPUSEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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clock-frequency = <1300000000>;
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};
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc32k: oscillator-1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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clock-output-names = "rtc32k";
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};
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clk26m: oscillator-0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <13000000>;
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arm,cpu-registers-not-fw-configured;
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};
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topckgen: clock-controller@10000000 {
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compatible = "mediatek,mt7623-topckgen";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt7623-infracfg", "syscon";
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reg = <0x10001000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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pericfg: syscon@10003000 {
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compatible = "mediatek,mt7623-pericfg", "syscon";
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reg = <0x10003000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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pinctrl: pinctrl@10005000 {
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compatible = "mediatek,mt7623-pinctrl";
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reg = <0x10005000 0x1000>;
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gpio: gpio-controller {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt7623-scpsys";
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#power-domain-cells = <1>;
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reg = <0x10006000 0x1000>;
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infracfg = <&infracfg>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_MFG_SEL>,
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<&topckgen CLK_TOP_ETHIF_SEL>;
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clock-names = "mm", "mfg", "ethif";
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,wdt";
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reg = <0x10007000 0x100>;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&watchdog>;
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};
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timer0: timer@10008000 {
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compatible = "mediatek,timer";
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reg = <0x10008000 0x80>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>;
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clock-names = "system-clk";
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u-boot,dm-pre-reloc;
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};
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10200100 0x1c>;
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};
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apmixedsys: clock-controller@10209000 {
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compatible = "mediatek,mt7623-apmixedsys";
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reg = <0x10209000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10211000 0x1000>,
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<0x10212000 0x1000>,
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<0x10214000 0x2000>,
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<0x10216000 0x2000>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,hsuart";
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reg = <0x11002000 0x400>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,hsuart";
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reg = <0x11003000 0x400>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART1>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,hsuart";
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reg = <0x11004000 0x400>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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uart3: serial@11005000 {
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compatible = "mediatek,hsuart";
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reg = <0x11005000 0x400>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART3>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt7623-mmc";
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reg = <0x11230000 0x1000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_MSDC30_0>,
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<&topckgen CLK_TOP_MSDC30_0_SEL>;
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clock-names = "source", "hclk";
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status = "disabled";
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};
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mmc1: mmc@11240000 {
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compatible = "mediatek,mt7623-mmc";
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reg = <0x11240000 0x1000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_MSDC30_1>,
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<&topckgen CLK_TOP_MSDC30_1_SEL>;
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clock-names = "source", "hclk";
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status = "disabled";
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};
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ethsys: syscon@1b000000 {
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compatible = "mediatek,mt7623-ethsys", "syscon";
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reg = <0x1b000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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eth: ethernet@1b100000 {
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compatible = "mediatek,mt7623-eth", "syscon";
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reg = <0x1b100000 0x20000>;
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clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
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<ðsys CLK_ETHSYS_ESW>,
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<ðsys CLK_ETHSYS_GP1>,
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<ðsys CLK_ETHSYS_GP2>,
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<&apmixedsys CLK_APMIXED_TRGPLL>;
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clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
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power-domains = <&scpsys MT7623_POWER_DOMAIN_ETH>;
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resets = <ðsys ETHSYS_FE_RST>,
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<ðsys ETHSYS_MCM_RST>;
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reset-names = "fe", "mcm";
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mediatek,ethsys = <ðsys>;
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status = "disabled";
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};
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};
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