u-boot/board/dbau1x00/Kconfig
Paul Burton 372286217f MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31 09:44:24 +02:00

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if TARGET_DBAU1X00
config SYS_BOARD
default "dbau1x00"
config SYS_SOC
default "au1x00"
config SYS_CONFIG_NAME
default "dbau1x00"
config SYS_TEXT_BASE
default 0xbfc00000
config SYS_DCACHE_SIZE
default 16384
config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 16384
config SYS_ICACHE_LINE_SIZE
default 32
menu "dbau1x00 board options"
choice
prompt "Select au1x00 SoC type"
optional
config DBAU1100
bool "Select AU1100"
config DBAU1500
bool "Select AU1500"
config DBAU1550
bool "Select AU1550"
endchoice
endmenu
endif