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0aa27657b0
interrupts.c: In function 'interrupt_init_cpu': interrupts.c:37: warning: implicit declaration of function 'GTREGREAD' interrupts.c:37: error: 'LOW_INTERRUPT_CAUSE_REGISTER' undeclared (first use in this function) interrupts.c:37: error: (Each undeclared identifier is reported only once interrupts.c:37: error: for each function it appears in.) interrupts.c:37: error: 'HIGH_INTERRUPT_CAUSE_REGISTER' undeclared (first use in this function) interrupts.c:40: error: 'ETHERNET0_INTERRUPT_CAUSE_REGISTER' undeclared (first use in this function) interrupts.c:40: error: 'ETHERNET1_INTERRUPT_CAUSE_REGISTER' undeclared (first use in this function) interrupts.c:40: error: 'ETHERNET2_INTERRUPT_CAUSE_REGISTER' undeclared (first use in this function) interrupts.c:44: error: 'ETHERNET0_INTERRUPT_MASK_REGISTER' undeclared (first use in this function) interrupts.c:44: error: 'ETHERNET1_INTERRUPT_MASK_REGISTER' undeclared (first use in this function) interrupts.c:44: error: 'ETHERNET2_INTERRUPT_MASK_REGISTER' undeclared (first use in this function) Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>
256 lines
7.9 KiB
C
256 lines
7.9 KiB
C
/*
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* (C) Copyright 2002-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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*
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* Configuration settings for the PCIPPC-2 board.
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*
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
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#define CONFIG_SYS_TEXT_BASE 0xfff00000
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_PREBOOT ""
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#define CONFIG_BOOTDELAY 5
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#ifndef __ASSEMBLY__
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#include <galileo/core.h>
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SNTP
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size
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*/
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFFF00000
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#define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000
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/* Maximum amount of RAM.
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*/
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#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */
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#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
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CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
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#define CONFIG_SYS_RAMBOOT
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_INIT_RAM_LOCK
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/*
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* Temporary buffer for serial data until the real serial driver
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* is initialised (memtest will destroy this buffer)
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*/
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#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR
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#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000
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/* SDRAM 0 - 256MB
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*/
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#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \
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BATU_BL_256M | BATU_VS | BATU_VP)
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/* SDRAM 1 - 256MB
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*/
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#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
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BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
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BATU_BL_256M | BATU_VS | BATU_VP)
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/* Init RAM in the CPU DCache (no backing memory)
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*/
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#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \
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BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \
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BATU_BL_128K | BATU_VS | BATU_VP)
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/* I/O and PCI memory at 0xf0000000
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*/
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#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L
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#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
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#define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L
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#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
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#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L
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#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
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#define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L
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#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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* For the detail description refer to the PCIPPC2 user's manual.
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*/
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */
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#define CONFIG_SYS_CPU_CLK 300000000
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
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/*
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* Note: environment is not EMBEDDED in the U-Boot code.
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* It's stored in flash separately.
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000)
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#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* L2 cache
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*/
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#undef CONFIG_SYS_L2
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#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
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L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
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#define L2_ENABLE (L2_INIT | L2CR_L2E)
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/*-----------------------------------------------------------------------
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RTC m48t59
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*/
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#define CONFIG_RTC_MK48T59
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#define CONFIG_WATCHDOG
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#define CONFIG_EEPRO100
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#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_TULIP
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#endif /* __CONFIG_H */
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