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f93ae788c3
Patch by Haavard Skinnemoen, 06 Sep 2006
This is a first attempt at creating a common serial driver for Atmel
chips. For now, it supports the AT32AP7000 AVR32 chip, but it should
be possible to support AT91RM9200 and other ARM-based chips with some
minor modifications.
There's nothing fundamentally AVR32-specific in this driver, but it
does use some features which are currently only defined for the
AT32AP CPU port:
* pm_get_clock_freq: Obtain the clock frequency of a given domain
* gd->console_uart: A "struct device" containing information about
register mappings, gpio resources and clocks associated with the
UART device.
For more information about these features, please see the "AT32AP
CPU" patch.
89 lines
2.3 KiB
C
89 lines
2.3 KiB
C
/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <common.h>
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#ifdef CONFIG_ATMEL_USART
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#include <asm/io.h>
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#include <asm/arch/platform.h>
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#include "atmel_usart.h"
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DECLARE_GLOBAL_DATA_PTR;
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void serial_setbrg(void)
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{
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unsigned long divisor;
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unsigned long usart_hz;
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/*
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* Master Clock
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* Baud Rate = --------------
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* 16 * CD
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*/
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usart_hz = pm_get_clock_freq(gd->console_uart->resource[0].u.clock.id);
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divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
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usart3_writel(gd->console_uart, BRGR, USART3_BF(CD, divisor));
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}
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int serial_init(void)
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{
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usart3_writel(gd->console_uart, CR,
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USART3_BIT(RSTRX) | USART3_BIT(RSTTX));
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serial_setbrg();
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usart3_writel(gd->console_uart, CR,
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USART3_BIT(RXEN) | USART3_BIT(TXEN));
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usart3_writel(gd->console_uart, MR,
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USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
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| USART3_BF(USCLKS, USART3_USCLKS_MCK)
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| USART3_BF(CHRL, USART3_CHRL_8)
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| USART3_BF(PAR, USART3_PAR_NONE)
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| USART3_BF(NBSTOP, USART3_NBSTOP_1));
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return 0;
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}
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void serial_putc(char c)
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{
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if (c == '\n')
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serial_putc('\r');
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while (!(usart3_readl(gd->console_uart, CSR) & USART3_BIT(TXRDY))) ;
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usart3_writel(gd->console_uart, THR, c);
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}
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void serial_puts(const char *s)
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{
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while (*s)
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serial_putc(*s++);
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}
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int serial_getc(void)
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{
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while (!(usart3_readl(gd->console_uart, CSR) & USART3_BIT(RXRDY))) ;
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return usart3_readl(gd->console_uart, RHR);
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}
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int serial_tstc(void)
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{
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return (usart3_readl(gd->console_uart, CSR) & USART3_BIT(RXRDY)) != 0;
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}
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#endif /* CONFIG_ATMEL_USART */
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