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The core specific part of the work is done in the assembly routine in nonsec_virt.S, introduced with the previous patch, but for the full glory we need to setup the GIC distributor interface once for the whole system, which is done in C here. The routine is placed in arch/arm/cpu/armv7 to allow easy access from other ARMv7 boards. We check the availability of the security extensions first. Since we need a safe way to access the GIC, we use the PERIPHBASE registers on Cortex-A15 and A7 CPUs and do some sanity checks. Boards not implementing the CBAR can override this value via a configuration file variable. Then we actually do the GIC enablement: a) enable the GIC distributor, both for non-secure and secure state (GICD_CTLR[1:0] = 11b) b) allow all interrupts to be handled from non-secure state (GICD_IGROUPRn = 0xFFFFFFFF) The core specific GIC setup is then done in the assembly routine. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> |
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arm720t | ||
arm920t | ||
arm925t | ||
arm926ejs | ||
arm946es | ||
arm1136 | ||
arm1176 | ||
arm_intcm | ||
armv7 | ||
ixp | ||
pxa | ||
sa1100 | ||
tegra20-common | ||
tegra30-common | ||
tegra114-common | ||
tegra-common | ||
u-boot-spl.lds | ||
u-boot.lds |