mirror of
https://github.com/u-boot/u-boot.git
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3e204427c8
Perform a simple rename of CONFIG_SMP_PEN_ADDR to CFG_SMP_PEN_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
273 lines
8.0 KiB
C
273 lines
8.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2019 NXP
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
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#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
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#ifdef CONFIG_NAND_BOOT
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#define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10)
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#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
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#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
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#endif
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#define SPD_EEPROM_ADDRESS 0x51
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#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
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/*
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* IFC Definitions
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*/
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CFG_SYS_FLASH_BASE 0x60000000
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#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
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#define CFG_SYS_NOR0_CSPR_EXT (0x0)
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#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CFG_SYS_NOR1_CSPR_EXT (0x0)
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#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
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+ 0x8000000) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
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#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_TRHZ_80)
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#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1a) | \
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0xe) | \
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FTIM2_NOR_TWP(0x1c))
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#define CFG_SYS_NOR_FTIM3 0
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#define CFG_SYS_WRITE_SWAPPED_DATA
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#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \
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CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
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/*
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* NAND Flash Definitions
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*/
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#define CFG_SYS_NAND_BASE 0x7e800000
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#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
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#define CFG_SYS_NAND_CSPR_EXT (0x0)
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#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_NAND \
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| CSPR_V)
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#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
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| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
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#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x7) | \
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FTIM0_NAND_TWH(0xa))
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#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0xe) | \
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FTIM1_NAND_TRP(0x18))
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#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
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FTIM2_NAND_TREH(0xa) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CFG_SYS_NAND_FTIM3 0x0
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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#endif
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/*
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* QIXIS Definitions
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*/
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#ifdef CONFIG_FSL_QIXIS
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#define QIXIS_BASE 0x7fb00000
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#define QIXIS_BASE_PHYS QIXIS_BASE
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#define CFG_SYS_I2C_FPGA_ADDR 0x66
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#define QIXIS_LBMAP_SWITCH 6
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SHIFT 0
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x04
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#define QIXIS_PWR_CTL 0x21
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#define QIXIS_PWR_CTL_POWEROFF 0x80
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#define QIXIS_RST_CTL_RESET 0x44
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define QIXIS_CTL_SYS 0x5
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#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
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#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
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#define QIXIS_RST_FORCE_3 0x45
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#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
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#define QIXIS_PWR_CTL2 0x21
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#define QIXIS_PWR_CTL2_PCTL 0x2
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#define CFG_SYS_FPGA_CSPR_EXT (0x0)
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#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
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#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_NOR_MODE_AVD_NOR | \
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CSOR_NOR_TRHZ_80)
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/*
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* QIXIS Timing parameters for IFC GPCM
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*/
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#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
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FTIM0_GPCM_TEADC(0xe) | \
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FTIM0_GPCM_TEAHC(0xe))
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#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
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FTIM1_GPCM_TRAD(0x1f))
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#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
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FTIM2_GPCM_TCH(0xe) | \
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FTIM2_GPCM_TWP(0xf0))
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#define CFG_SYS_FPGA_FTIM3 0x0
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#endif
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#if defined(CONFIG_NAND_BOOT)
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#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
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#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
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#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
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#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
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#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
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#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
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#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
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#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
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#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
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#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
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#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
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#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
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#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
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#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
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#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
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#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
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#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
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#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
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#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
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#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
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#else
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#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
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#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
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#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
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#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
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#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
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#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
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#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
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#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
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#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
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#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
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#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
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#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
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#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
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#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
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#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
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#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
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#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
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#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
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#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
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#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
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#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
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#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
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#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
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#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
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#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
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#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
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#endif
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/*
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* Serial Port
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*/
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#ifndef CONFIG_LPUART
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#define CFG_SYS_NS16550_CLK get_serial_clock()
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#endif
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/*
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* I2C
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*/
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/* GPIO */
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/*
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* I2C bus multiplexer
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*/
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#define I2C_MUX_PCA_ADDR_PRI 0x77
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#define I2C_MUX_CH_DEFAULT 0x8
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#define I2C_MUX_CH_CH7301 0xC
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/*
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* MMC
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*/
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#define CFG_SMP_PEN_ADDR 0x01ee0200
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#define HWCONFIG_BUFFER_SIZE 256
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#ifdef CONFIG_LPUART
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#define CFG_EXTRA_ENV_SETTINGS \
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"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
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"initrd_high=0xffffffff\0" \
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"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
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#else
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#define CFG_EXTRA_ENV_SETTINGS \
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"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
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"initrd_high=0xffffffff\0" \
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"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_SYS_BOOTMAPSZ (256 << 20)
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/*
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* Environment
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*/
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#include <asm/fsl_secure_boot.h>
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#endif
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