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baf37f06c5
This patch adds support for running on Malta boards using coreFPGA6
core cards, including support for the msc01 system controller used
with them. The system controller is detected at runtime allowing one
U-boot binary to run on a Malta with either.
Due to the PCI I/O base differing between Maltas using gt64120 & msc01
system controllers, the UART setup is modified slightly. A second UART
is added so that there is one pointing at the correct address for each
system controller. The Malta board then defines its own
default_serial_console function to select the correct one at runtime.
The incorrect UART will simply not function.
Tested on:
- A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both
with and without an L2 cache.
- QEMU.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
116 lines
2.6 KiB
C
116 lines
2.6 KiB
C
/*
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _MALTA_CONFIG_H
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#define _MALTA_CONFIG_H
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#include <asm/addrspace.h>
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#include <asm/malta.h>
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/*
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* System configuration
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*/
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#define CONFIG_MALTA
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#define CONFIG_PCI
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#define CONFIG_PCI_GT64120
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#define CONFIG_PCI_MSC01
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#define CONFIG_PCI_PNP
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#define CONFIG_PCNET
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/*
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* CPU Configuration
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*/
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#define CONFIG_SYS_MHZ 250 /* arbitrary value */
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#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
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#define CONFIG_SYS_DCACHE_SIZE 16384 /* arbitrary value */
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#define CONFIG_SYS_ICACHE_SIZE 16384 /* arbitrary value */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* arbitrary value */
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#define CONFIG_SWAP_IO_SPACE
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/*
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* Memory map
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*/
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#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
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#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
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#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
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#define CONFIG_SYS_LOAD_ADDR 0x81000000
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#define CONFIG_SYS_MEMTEST_START 0x80100000
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#define CONFIG_SYS_MEMTEST_END 0x80800000
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
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#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
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/*
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* Console configuration
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*/
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#if defined(CONFIG_SYS_LITTLE_ENDIAN)
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#define CONFIG_SYS_PROMPT "maltael # "
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#else
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#define CONFIG_SYS_PROMPT "malta # "
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#endif
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_CMDLINE_EDITING
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/*
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* Serial driver
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*/
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK 115200
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#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE)
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#define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE)
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#define CONFIG_CONS_INDEX 1
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_ENV_SIZE 0x10000
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/*
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* Flash configuration
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*/
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#define CONFIG_SYS_FLASH_BASE (KSEG1 | MALTA_FLASH_BASE)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 128
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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/*
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* Commands
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_LOADB
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */
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#endif /* _MALTA_CONFIG_H */
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