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125 lines
3.6 KiB
C
125 lines
3.6 KiB
C
/*
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* Copyright (C) 2004-2005 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* Support for Analogue&Micro Adder boards family.
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* Tested on AdderII and Adder87x.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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/*
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* SDRAM is single Samsung K4S643232F-T70 chip (8MB)
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* or single Micron MT48LC4M32B2TG-7 chip (16MB).
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* Minimal CPU frequency is 40MHz.
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*/
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static uint sdram_table[] = {
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/* Single read (offset 0x00 in UPM RAM) */
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0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
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0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
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/* Burst read (offset 0x08 in UPM RAM) */
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0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
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0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
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0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
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0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
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/* Single write (offset 0x18 in UPM RAM) */
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0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
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0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* Burst write (offset 0x20 in UPM RAM) */
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0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
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0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* Refresh (offset 0x30 in UPM RAM) */
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0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* Exception (offset 0x3C in UPM RAM) */
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0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
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};
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phys_size_t initdram (int board_type)
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{
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long int msize;
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volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
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/* Configure SDRAM refresh */
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memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
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memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
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udelay(200);
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/* Run precharge from location 0x15 */
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memctl->memc_mar = 0x0;
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memctl->memc_mcr = 0x80002115;
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udelay(200);
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/* Run 8 refresh cycles */
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memctl->memc_mcr = 0x80002830;
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udelay(200);
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/* Run MRS pattern from location 0x16 */
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memctl->memc_mar = 0x88;
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memctl->memc_mcr = 0x80002116;
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udelay(200);
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memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
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memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
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memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
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msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
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memctl->memc_or1 |= ~(msize - 1);
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return msize;
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}
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int checkboard( void )
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{
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puts("Board: Adder");
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#if defined(CONFIG_MPC885_FAMILY)
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puts("87x\n");
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#elif defined(CONFIG_MPC866_FAMILY)
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puts("II\n");
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#endif
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif
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