mirror of
https://github.com/u-boot/u-boot.git
synced 2024-12-20 18:23:25 +08:00
f89d6133ee
Moved CONFIG_SPL_TEXT_BASE to common/spl/Kconfig and migrate existing values. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Re-run migration] Signed-off-by: Tom Rini <trini@konsulko.com>
108 lines
2.9 KiB
C
108 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* (C) Copyright 2013
|
|
* Texas Instruments Incorporated.
|
|
* Sricharan R <r.sricharan@ti.com>
|
|
*
|
|
* Derived from OMAP4 done by:
|
|
* Aneesh V <aneesh@ti.com>
|
|
*
|
|
* TI OMAP5 AND DRA7XX common configuration settings
|
|
*
|
|
* For more details, please see the technical documents listed at
|
|
* http://www.ti.com/product/omap5432
|
|
*/
|
|
|
|
#ifndef __CONFIG_TI_OMAP5_COMMON_H
|
|
#define __CONFIG_TI_OMAP5_COMMON_H
|
|
|
|
/* Use General purpose timer 1 */
|
|
#define CONFIG_SYS_TIMERBASE GPT2_BASE
|
|
|
|
/*
|
|
* For the DDR timing information we can either dynamically determine
|
|
* the timings to use or use pre-determined timings (based on using the
|
|
* dynamic method. Default to the static timing infomation.
|
|
*/
|
|
#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
|
|
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
|
|
#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
|
|
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
|
|
#endif
|
|
|
|
#define CONFIG_PALMAS_POWER
|
|
|
|
#include <asm/arch/cpu.h>
|
|
#include <asm/arch/omap.h>
|
|
|
|
#include <configs/ti_armv7_omap.h>
|
|
|
|
/*
|
|
* Hardware drivers
|
|
*/
|
|
#define CONFIG_SYS_NS16550_CLK 48000000
|
|
#if !defined(CONFIG_DM_SERIAL)
|
|
#define CONFIG_SYS_NS16550_SERIAL
|
|
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
|
#endif
|
|
|
|
/*
|
|
* Environment setup
|
|
*/
|
|
|
|
#ifndef DFUARGS
|
|
#define DFUARGS
|
|
#endif
|
|
|
|
#include <environment/ti/boot.h>
|
|
#include <environment/ti/mmc.h>
|
|
#include <environment/ti/nand.h>
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
DEFAULT_LINUX_BOOT_ENV \
|
|
DEFAULT_MMC_TI_ARGS \
|
|
DEFAULT_FIT_TI_ARGS \
|
|
DEFAULT_COMMON_BOOT_TI_ARGS \
|
|
DEFAULT_FDT_TI_ARGS \
|
|
DFUARGS \
|
|
NETARGS \
|
|
NANDARGS \
|
|
|
|
/*
|
|
* SPL related defines. The Public RAM memory map the ROM defines the
|
|
* area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
|
|
* On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
|
|
* We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
|
|
* print some information.
|
|
*/
|
|
#ifdef CONFIG_TI_SECURE_DEVICE
|
|
/*
|
|
* For memory booting on HS parts, the first 4KB of the internal RAM is
|
|
* reserved for secure world use and the flash loader image is
|
|
* preceded by a secure certificate. The SPL will therefore run in internal
|
|
* RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
|
|
*/
|
|
#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000
|
|
/* If no specific start address is specified then the secure EMIF
|
|
* region will be placed at the end of the DDR space. In order to prevent
|
|
* the main u-boot relocation from clobbering that memory and causing a
|
|
* firewall violation, we tell u-boot that memory is protected RAM (PRAM)
|
|
*/
|
|
#if (CONFIG_TI_SECURE_EMIF_REGION_START == 0)
|
|
#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10
|
|
#endif
|
|
#else
|
|
/*
|
|
* For all booting on GP parts, the flash loader image is
|
|
* downloaded into internal RAM at address 0x40300000.
|
|
*/
|
|
#endif
|
|
|
|
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
|
|
(128 << 20))
|
|
#ifdef CONFIG_SPL_BUILD
|
|
#undef CONFIG_TIMER
|
|
#endif
|
|
|
|
#endif /* __CONFIG_TI_OMAP5_COMMON_H */
|