mirror of
https://github.com/u-boot/u-boot.git
synced 2024-12-20 18:23:25 +08:00
5dc1dc804d
The L4T kernel is 32MB+, and can overwrite the ramdisk/fdt loaded from extlinux.conf. Adjust the load addresses to fix this for now. Using the calculated_env addresses table from T186 U-Boot is a better fix, but it isn't working correctly on T210 U-Boot right now, so this will do until I can fix it. Signed-off-by: Tom Warren <twarren@nvidia.com>
60 lines
1.9 KiB
C
60 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* (C) Copyright 2013-2015
|
|
* NVIDIA Corporation <www.nvidia.com>
|
|
*/
|
|
|
|
#ifndef _TEGRA210_COMMON_H_
|
|
#define _TEGRA210_COMMON_H_
|
|
|
|
#include "tegra-common.h"
|
|
|
|
/*
|
|
* NS16550 Configuration
|
|
*/
|
|
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
|
|
|
|
/* Generic Interrupt Controller */
|
|
#define CONFIG_GICV2
|
|
|
|
/*
|
|
* Memory layout for where various images get loaded by boot scripts:
|
|
*
|
|
* scriptaddr can be pretty much anywhere that doesn't conflict with something
|
|
* else. Put it above BOOTMAPSZ to eliminate conflicts.
|
|
*
|
|
* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
|
|
* something else. Put it above BOOTMAPSZ to eliminate conflicts.
|
|
*
|
|
* kernel_addr_r must be within the first 128M of RAM in order for the
|
|
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
|
|
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
|
|
* should not overlap that area, or the kernel will have to copy itself
|
|
* somewhere else before decompression. Similarly, the address of any other
|
|
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
|
|
* this up to 16M allows for a sizable kernel to be decompressed below the
|
|
* compressed load address.
|
|
*
|
|
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
|
|
* the compressed kernel to be up to 16M too.
|
|
*
|
|
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
|
|
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
|
|
*/
|
|
#define CONFIG_LOADADDR 0x80080000
|
|
#define MEM_LAYOUT_ENV_SETTINGS \
|
|
"scriptaddr=0x90000000\0" \
|
|
"pxefile_addr_r=0x90100000\0" \
|
|
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
|
|
"fdt_addr_r=0x83000000\0" \
|
|
"ramdisk_addr_r=0x83200000\0"
|
|
|
|
/* For USB EHCI controller */
|
|
#define CONFIG_EHCI_IS_TDI
|
|
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
|
|
|
|
/* GPU needs setup */
|
|
#define CONFIG_TEGRA_GPU
|
|
|
|
#endif /* _TEGRA210_COMMON_H_ */
|