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702de89cc6
Move below defines which are used by mtest utility to Kconfig. CONFIG_SYS_MEMTEST_START CONFIG_SYS_MEMTEST_END Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Fix kmcoge5ne board, re-run migration as well] Signed-off-by: Tom Rini <trini@konsulko.com>
285 lines
9.0 KiB
C
285 lines
9.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2008
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
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*
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* Wolfgang Denk <wd@denx.de>
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2002,2003 Motorola,Inc.
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* Xianghua Xiao <X.Xiao@motorola.com>
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*/
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/*
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* Socrates
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_SOCRATES 1
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/*
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* Only possible on E500 Version 2 or newer cores.
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*/
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#define CONFIG_ENABLE_36BIT_PHYS 1
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/*
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* sysclk for MPC85xx
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*
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* Two valid values are:
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* 33000000
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* 66000000
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*
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* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
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* is likely the desired value here, so that is now the default.
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* The board, however, can run at 66MHz. In any event, this value
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* must match the settings of some switches. Details can be found
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* in the README.mpc85xxads.
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*/
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ 66666666
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#endif
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#define CONFIG_SYS_CCSRBAR 0xE0000000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* DDR Setup */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#define CONFIG_DDR_SPD
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#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 2
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/* I2C addresses of SPD EEPROMs */
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#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
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#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
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/* Hardcoded values, to use instead of SPD */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
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#define CONFIG_SYS_DDR_TIMING_0 0x00260802
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#define CONFIG_SYS_DDR_TIMING_1 0x3935D322
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#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
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#define CONFIG_SYS_DDR_MODE 0x00480432
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#define CONFIG_SYS_DDR_INTERVAL 0x030C0100
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#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
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#define CONFIG_SYS_DDR_CONFIG 0xC3008000
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#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
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#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
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/*
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* Flash on the LocalBus
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*/
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#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_SYS_FLASH0 0xFE000000
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#define CONFIG_SYS_FLASH1 0xFC000000
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
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#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
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#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
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#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
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#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
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#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
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#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
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#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
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/* FPGA and NAND */
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#define CONFIG_SYS_FPGA_BASE 0xc0000000
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#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
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#define CONFIG_SYS_HMI_BASE 0xc0010000
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#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
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#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
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#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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/* LIME GDC */
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#define CONFIG_SYS_LIME_BASE 0xc8000000
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#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
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#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
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#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
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/*
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* General PCI
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* Memory space is mapped 1-1.
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*/
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/* PCI is clocked by the external source at 33 MHz */
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#define CONFIG_PCI_CLK_FREQ 33000000
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
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#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
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#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "TSEC1"
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#undef CONFIG_MPC85XX_FEC
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#define TSEC1_PHY_ADDR 0
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#define TSEC3_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC3_FLAGS TSEC_GIGABIT
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/* Options are: TSEC[0,1] */
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#define CONFIG_ETHPRIME "TSEC0"
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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/*
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* Environment
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*/
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_TIMESTAMP /* Print image info with ts */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
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#endif
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#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consdev=ttyS0\0" \
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"uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
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"bootfile=/home/tftp/syscon3/uImage\0" \
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"fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
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"initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
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"uboot_addr=FFF60000\0" \
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"kernel_addr=FE000000\0" \
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"fdt_addr=FE1E0000\0" \
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"ramdisk_addr=FE200000\0" \
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"fdt_addr_r=B00000\0" \
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"kernel_addr_r=200000\0" \
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"ramdisk_addr_r=400000\0" \
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"rootpath=/opt/eldk/ppc_85xxDP\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath\0" \
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"addcons=setenv bootargs $bootargs " \
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"console=$consdev,$baudrate\0" \
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"addip=setenv bootargs $bootargs " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
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":$hostname:$netdev:off panic=1\0" \
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"boot_nor=run ramargs addcons;" \
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"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
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"tftp ${fdt_addr_r} ${fdt_file}; " \
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"run nfsargs addip addcons;" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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"update_uboot=tftp 100000 ${uboot_file};" \
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"protect off fff60000 ffffffff;" \
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"era fff60000 ffffffff;" \
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"cp.b 100000 fff60000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"update_kernel=tftp 100000 ${bootfile};" \
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"era fe000000 fe1dffff;" \
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"cp.b 100000 fe000000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"update_fdt=tftp 100000 ${fdt_file};" \
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"era fe1e0000 fe1fffff;" \
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"cp.b 100000 fe1e0000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"update_initrd=tftp 100000 ${initrd_file};" \
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"era fe200000 fe9fffff;" \
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"cp.b 100000 fe200000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"clean_data=era fea00000 fff5ffff\0" \
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"usbargs=setenv bootargs root=/dev/sda1 rw\0" \
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"load_usb=usb start;" \
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"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
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"boot_usb=run load_usb usbargs addcons;" \
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"bootm ${kernel_addr_r} - ${fdt_addr};" \
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"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
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""
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#define CONFIG_BOOTCOMMAND "run boot_nor"
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/* pass open firmware flat tree */
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/* USB support */
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_PCI_OHCI 1
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
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#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
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#endif /* __CONFIG_H */
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