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81 lines
2.5 KiB
C
81 lines
2.5 KiB
C
/*
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* Faraday I2C Controller
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*
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* (C) Copyright 2010 Faraday Technology
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* Dante Su <dantesu@faraday-tech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FTI2C010_H
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#define __FTI2C010_H
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/*
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* FTI2C010 registers
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*/
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struct fti2c010_regs {
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uint32_t cr; /* 0x00: control register */
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uint32_t sr; /* 0x04: status register */
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uint32_t cdr; /* 0x08: clock division register */
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uint32_t dr; /* 0x0c: data register */
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uint32_t sar; /* 0x10: slave address register */
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uint32_t tgsr;/* 0x14: time & glitch suppression register */
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uint32_t bmr; /* 0x18: bus monitor register */
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uint32_t rsvd[5];
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uint32_t revr;/* 0x30: revision register */
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};
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/*
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* control register
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*/
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#define CR_ALIRQ 0x2000 /* arbitration lost interrupt (master) */
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#define CR_SAMIRQ 0x1000 /* slave address match interrupt (slave) */
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#define CR_STOPIRQ 0x800 /* stop condition interrupt (slave) */
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#define CR_NAKRIRQ 0x400 /* NACK response interrupt (master) */
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#define CR_DRIRQ 0x200 /* rx interrupt (both) */
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#define CR_DTIRQ 0x100 /* tx interrupt (both) */
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#define CR_TBEN 0x80 /* tx enable (both) */
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#define CR_NAK 0x40 /* NACK (both) */
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#define CR_STOP 0x20 /* stop (master) */
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#define CR_START 0x10 /* start (master) */
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#define CR_GCEN 0x8 /* general call support (slave) */
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#define CR_SCLEN 0x4 /* enable clock out (master) */
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#define CR_I2CEN 0x2 /* enable I2C (both) */
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#define CR_I2CRST 0x1 /* reset I2C (both) */
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#define CR_ENABLE \
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(CR_ALIRQ | CR_NAKRIRQ | CR_DRIRQ | CR_DTIRQ | CR_SCLEN | CR_I2CEN)
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/*
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* status register
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*/
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#define SR_CLRAL 0x400 /* clear arbitration lost */
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#define SR_CLRGC 0x200 /* clear general call */
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#define SR_CLRSAM 0x100 /* clear slave address match */
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#define SR_CLRSTOP 0x80 /* clear stop */
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#define SR_CLRNAKR 0x40 /* clear NACK respond */
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#define SR_DR 0x20 /* rx ready */
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#define SR_DT 0x10 /* tx done */
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#define SR_BB 0x8 /* bus busy */
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#define SR_BUSY 0x4 /* chip busy */
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#define SR_ACK 0x2 /* ACK/NACK received */
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#define SR_RW 0x1 /* set when master-rx or slave-tx mode */
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/*
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* clock division register
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*/
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#define CDR_DIV(n) ((n) & 0x3ffff)
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/*
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* time & glitch suppression register
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*/
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#define TGSR_GSR(n) (((n) & 0x7) << 10)
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#define TGSR_TSR(n) ((n) & 0x3ff)
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/*
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* bus monitor register
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*/
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#define BMR_SCL 0x2 /* SCL is pull-up */
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#define BMR_SDA 0x1 /* SDA is pull-up */
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#endif /* __FTI2C010_H */
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