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b5a6c94a03
If north bridge selection register bit1 is clear, pins [10:8] are for SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn and CTSn, so bit1 should be added to uart2 group and it must be set for both "gpio" and "uart" functions of uart2 group. Signed-off-by: Ken Ma <make@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> |
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| .. | ||
| aspeed | ||
| ath79 | ||
| exynos | ||
| meson | ||
| mvebu | ||
| nxp | ||
| rockchip | ||
| uniphier | ||
| Kconfig | ||
| Makefile | ||
| pinctrl_pic32.c | ||
| pinctrl_stm32.c | ||
| pinctrl-at91-pio4.c | ||
| pinctrl-at91.c | ||
| pinctrl-generic.c | ||
| pinctrl-sandbox.c | ||
| pinctrl-single.c | ||
| pinctrl-sti.c | ||
| pinctrl-uclass.c | ||