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https://github.com/u-boot/u-boot.git
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400558b561
- rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL - rename memsetup into lowlevel_init (function name and source files)
386 lines
8.2 KiB
ArmAsm
386 lines
8.2 KiB
ArmAsm
/*
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* Startup Code for MIPS32 CPU-core
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*
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#define RVECENT(f,n) \
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b f; nop
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#define XVECENT(f,bev) \
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b f ; \
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li k0,bev
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.set noreorder
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.globl _start
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.text
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_start:
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RVECENT(reset,0) /* U-boot entry point */
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RVECENT(reset,1) /* software reboot */
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#if defined(CONFIG_INCA_IP)
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.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
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.word 0x00000000 /* phase of the flash */
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#elif defined(CONFIG_PURPLE)
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.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
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.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
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#else
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RVECENT(romReserved,2)
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#endif
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RVECENT(romReserved,3)
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RVECENT(romReserved,4)
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RVECENT(romReserved,5)
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RVECENT(romReserved,6)
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RVECENT(romReserved,7)
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RVECENT(romReserved,8)
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RVECENT(romReserved,9)
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RVECENT(romReserved,10)
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RVECENT(romReserved,11)
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RVECENT(romReserved,12)
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RVECENT(romReserved,13)
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RVECENT(romReserved,14)
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RVECENT(romReserved,15)
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RVECENT(romReserved,16)
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RVECENT(romReserved,17)
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RVECENT(romReserved,18)
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RVECENT(romReserved,19)
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RVECENT(romReserved,20)
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RVECENT(romReserved,21)
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RVECENT(romReserved,22)
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RVECENT(romReserved,23)
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RVECENT(romReserved,24)
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RVECENT(romReserved,25)
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RVECENT(romReserved,26)
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RVECENT(romReserved,27)
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RVECENT(romReserved,28)
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RVECENT(romReserved,29)
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RVECENT(romReserved,30)
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RVECENT(romReserved,31)
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RVECENT(romReserved,32)
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RVECENT(romReserved,33)
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RVECENT(romReserved,34)
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RVECENT(romReserved,35)
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RVECENT(romReserved,36)
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RVECENT(romReserved,37)
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RVECENT(romReserved,38)
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RVECENT(romReserved,39)
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RVECENT(romReserved,40)
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RVECENT(romReserved,41)
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RVECENT(romReserved,42)
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RVECENT(romReserved,43)
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RVECENT(romReserved,44)
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RVECENT(romReserved,45)
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RVECENT(romReserved,46)
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RVECENT(romReserved,47)
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RVECENT(romReserved,48)
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RVECENT(romReserved,49)
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RVECENT(romReserved,50)
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RVECENT(romReserved,51)
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RVECENT(romReserved,52)
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RVECENT(romReserved,53)
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RVECENT(romReserved,54)
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RVECENT(romReserved,55)
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RVECENT(romReserved,56)
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RVECENT(romReserved,57)
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RVECENT(romReserved,58)
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RVECENT(romReserved,59)
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RVECENT(romReserved,60)
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RVECENT(romReserved,61)
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RVECENT(romReserved,62)
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RVECENT(romReserved,63)
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XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
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RVECENT(romReserved,65)
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RVECENT(romReserved,66)
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RVECENT(romReserved,67)
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RVECENT(romReserved,68)
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RVECENT(romReserved,69)
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RVECENT(romReserved,70)
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RVECENT(romReserved,71)
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RVECENT(romReserved,72)
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RVECENT(romReserved,73)
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RVECENT(romReserved,74)
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RVECENT(romReserved,75)
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RVECENT(romReserved,76)
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RVECENT(romReserved,77)
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RVECENT(romReserved,78)
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RVECENT(romReserved,79)
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XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
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RVECENT(romReserved,81)
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RVECENT(romReserved,82)
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RVECENT(romReserved,83)
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RVECENT(romReserved,84)
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RVECENT(romReserved,85)
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RVECENT(romReserved,86)
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RVECENT(romReserved,87)
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RVECENT(romReserved,88)
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RVECENT(romReserved,89)
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RVECENT(romReserved,90)
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RVECENT(romReserved,91)
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RVECENT(romReserved,92)
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RVECENT(romReserved,93)
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RVECENT(romReserved,94)
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RVECENT(romReserved,95)
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XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
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RVECENT(romReserved,97)
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RVECENT(romReserved,98)
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RVECENT(romReserved,99)
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RVECENT(romReserved,100)
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RVECENT(romReserved,101)
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RVECENT(romReserved,102)
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RVECENT(romReserved,103)
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RVECENT(romReserved,104)
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RVECENT(romReserved,105)
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RVECENT(romReserved,106)
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RVECENT(romReserved,107)
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RVECENT(romReserved,108)
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RVECENT(romReserved,109)
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RVECENT(romReserved,110)
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RVECENT(romReserved,111)
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XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
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RVECENT(romReserved,113)
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RVECENT(romReserved,114)
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RVECENT(romReserved,115)
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RVECENT(romReserved,116)
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RVECENT(romReserved,116)
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RVECENT(romReserved,118)
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RVECENT(romReserved,119)
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RVECENT(romReserved,120)
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RVECENT(romReserved,121)
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RVECENT(romReserved,122)
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RVECENT(romReserved,123)
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RVECENT(romReserved,124)
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RVECENT(romReserved,125)
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RVECENT(romReserved,126)
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RVECENT(romReserved,127)
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/* We hope there are no more reserved vectors!
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* 128 * 8 == 1024 == 0x400
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* so this is address R_VEC+0x400 == 0xbfc00400
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*/
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#ifdef CONFIG_PURPLE
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/* 0xbfc00400 */
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.word 0xdc870000
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.word 0xfca70000
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.word 0x20840008
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.word 0x20a50008
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.word 0x20c6ffff
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.word 0x14c0fffa
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.word 0x00000000
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.word 0x03e00008
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.word 0x00000000
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.word 0x00000000
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/* 0xbfc00428 */
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.word 0xdc870000
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.word 0xfca70000
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.word 0x20840008
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.word 0x20a50008
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.word 0x20c6ffff
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.word 0x14c0fffa
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.word 0x00000000
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.word 0x03e00008
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.word 0x00000000
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.word 0x00000000
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#endif /* CONFIG_PURPLE */
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.align 4
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reset:
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/* Clear watch registers.
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*/
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mtc0 zero, CP0_WATCHLO
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mtc0 zero, CP0_WATCHHI
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/* STATUS register */
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#ifdef CONFIG_TB0229
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li k0, ST0_CU0
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#else
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mfc0 k0, CP0_STATUS
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#endif
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li k1, ~ST0_IE
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and k0, k1
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mtc0 k0, CP0_STATUS
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/* CAUSE register */
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mtc0 zero, CP0_CAUSE
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/* Init Timer */
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mtc0 zero, CP0_COUNT
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mtc0 zero, CP0_COMPARE
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/* CONFIG0 register */
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li t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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#ifdef CONFIG_INCA_IP
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/* Disable INCA-IP Watchdog.
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*/
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bal disable_incaip_wdt
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nop
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#endif
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/* Initialize any external memory.
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*/
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bal lowlevel_init
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nop
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/* Initialize caches...
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*/
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bal mips_cache_reset
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nop
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/* ... and enable them.
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*/
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li t0, CONF_CM_CACHABLE_NONCOHERENT
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mtc0 t0, CP0_CONFIG
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/* Set up temporary stack.
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*/
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li a0, CFG_INIT_SP_OFFSET
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bal mips_cache_lock
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nop
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li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
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la sp, 0(t0)
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/* Initialize GOT pointer.
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*/
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bal 1f
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nop
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.word _GLOBAL_OFFSET_TABLE_ - 1f + 4
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1:
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move gp, ra
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lw t1, 0(ra)
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add gp, t1
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la t9, board_init_f
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j t9
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nop
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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* a0 = addr_sp
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* a1 = gd
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* a2 = destination address
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*/
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.globl relocate_code
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.ent relocate_code
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relocate_code:
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move sp, a0 /* Set new stack pointer */
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li t0, CFG_MONITOR_BASE
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la t3, in_ram
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lw t2, -12(t3) /* t2 <-- uboot_end_data */
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move t1, a2
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/*
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* Fix GOT pointer:
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*
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* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
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*/
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move t6, gp
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sub gp, CFG_MONITOR_BASE
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add gp, a2 /* gp now adjusted */
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sub t6, gp, t6 /* t6 <-- relocation offset */
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/*
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* t0 = source address
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* t1 = target address
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* t2 = source end address
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*/
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/* On the purple board we copy the code earlier in a special way
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* in order to solve flash problems
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*/
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#ifndef CONFIG_PURPLE
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1:
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lw t3, 0(t0)
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sw t3, 0(t1)
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addu t0, 4
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ble t0, t2, 1b
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addu t1, 4 /* delay slot */
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#endif
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/* If caches were enabled, we would have to flush them here.
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*/
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/* Jump to where we've relocated ourselves.
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*/
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addi t0, a2, in_ram - _start
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j t0
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nop
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.word uboot_end_data
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.word uboot_end
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.word num_got_entries
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in_ram:
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/* Now we want to update GOT.
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*/
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lw t3, -4(t0) /* t3 <-- num_got_entries */
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addi t4, gp, 8 /* Skipping first two entries. */
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li t2, 2
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1:
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lw t1, 0(t4)
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beqz t1, 2f
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add t1, t6
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sw t1, 0(t4)
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2:
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addi t2, 1
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blt t2, t3, 1b
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addi t4, 4 /* delay slot */
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/* Clear BSS.
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*/
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lw t1, -12(t0) /* t1 <-- uboot_end_data */
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lw t2, -8(t0) /* t2 <-- uboot_end */
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add t1, t6 /* adjust pointers */
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add t2, t6
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sub t1, 4
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1: addi t1, 4
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bltl t1, t2, 1b
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sw zero, 0(t1) /* delay slot */
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move a0, a1
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la t9, board_init_r
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j t9
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move a1, a2 /* delay slot */
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.end relocate_code
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/* Exception handlers.
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*/
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romReserved:
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b romReserved
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romExcHandle:
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b romExcHandle
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