mirror of
https://github.com/u-boot/u-boot.git
synced 2024-11-25 05:04:23 +08:00
691d719db7
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
119 lines
2.7 KiB
C
119 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* SPL specific code for CCV xPress
|
|
*
|
|
* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <init.h>
|
|
#include <spl.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/mx6-ddr.h>
|
|
#include <asm/arch/crm_regs.h>
|
|
|
|
/* Configuration for IM IME1G16D3EEBG-15EI, 64M x 16 -> 128MiB */
|
|
|
|
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
|
|
.grp_addds = 0x00000030,
|
|
.grp_ddrmode_ctl = 0x00020000,
|
|
.grp_b0ds = 0x00000030,
|
|
.grp_ctlds = 0x00000030,
|
|
.grp_b1ds = 0x00000030,
|
|
.grp_ddrpke = 0x00000000,
|
|
.grp_ddrmode = 0x00020000,
|
|
.grp_ddr_type = 0x000c0000,
|
|
};
|
|
|
|
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
|
|
.dram_dqm0 = 0x00000030,
|
|
.dram_dqm1 = 0x00000030,
|
|
.dram_ras = 0x00000030,
|
|
.dram_cas = 0x00000030,
|
|
.dram_odt0 = 0x00000030,
|
|
.dram_odt1 = 0x00000030,
|
|
.dram_sdba2 = 0x00000000,
|
|
.dram_sdclk_0 = 0x00000008,
|
|
.dram_sdqs0 = 0x00000038,
|
|
.dram_sdqs1 = 0x00000030,
|
|
.dram_reset = 0x00000030,
|
|
};
|
|
|
|
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
|
.p0_mpwldectrl0 = 0x00000000,
|
|
.p0_mpdgctrl0 = 0x4164015C,
|
|
.p0_mprddlctl = 0x40404446,
|
|
.p0_mpwrdlctl = 0x40405A52,
|
|
};
|
|
|
|
struct mx6_ddr_sysinfo ddr_sysinfo = {
|
|
.dsize = 0,
|
|
.cs_density = 20,
|
|
.ncs = 1,
|
|
.cs1_mirror = 0,
|
|
.rtt_wr = 2,
|
|
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
|
|
.walat = 1, /* Write additional latency */
|
|
.ralat = 5, /* Read additional latency */
|
|
.mif3_mode = 3, /* Command prediction working mode */
|
|
.bi_on = 1, /* Bank interleaving enabled */
|
|
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
|
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
|
.ddr_type = DDR_TYPE_DDR3,
|
|
.refsel = 1, /* Refresh cycles at 32KHz */
|
|
.refr = 7, /* 8 refresh commands per refresh cycle */
|
|
};
|
|
|
|
static struct mx6_ddr3_cfg mem_ddr = {
|
|
.mem_speed = 800,
|
|
.density = 4,
|
|
.width = 16,
|
|
.banks = 8,
|
|
.rowaddr = 13,
|
|
.coladdr = 10,
|
|
.pagesz = 2,
|
|
.trcd = 1375,
|
|
.trcmin = 4875,
|
|
.trasmin = 3500,
|
|
};
|
|
|
|
static void ccgr_init(void)
|
|
{
|
|
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
writel(0xFFFFFFFF, &ccm->CCGR0);
|
|
writel(0xFFFFFFFF, &ccm->CCGR1);
|
|
writel(0xFFFFFFFF, &ccm->CCGR2);
|
|
writel(0xFFFFFFFF, &ccm->CCGR3);
|
|
writel(0xFFFFFFFF, &ccm->CCGR4);
|
|
writel(0xFFFFFFFF, &ccm->CCGR5);
|
|
writel(0xFFFFFFFF, &ccm->CCGR6);
|
|
writel(0xFFFFFFFF, &ccm->CCGR7);
|
|
}
|
|
|
|
static void spl_dram_init(void)
|
|
{
|
|
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
|
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
/* Setup AIPS and disable watchdog */
|
|
arch_cpu_init();
|
|
|
|
ccgr_init();
|
|
|
|
/* Setup iomux and i2c */
|
|
board_early_init_f();
|
|
|
|
/* Setup GP timer */
|
|
timer_init();
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
/* DDR initialization */
|
|
spl_dram_init();
|
|
}
|