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b2e6ad451b
When a high speed card is connected to mx51evk the following error is seen: U-Boot 2017.11-rc2 (Oct 18 2017 - 13:49:26 -0200) CPU: Freescale i.MX51 rev3.0 at 800 MHz Reset cause: POR Board: MX51EVK DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - read failed, using default environment In: serial Out: serial Err: serial Net: FEC Hit any key to stop autoboot: 0 => saveenv Saving Environment to MMC... Writing to MMC(0)... failed The root cause for the failure is the eSDHC-A001 erratum: "eSDHC-A001 : Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 0x4,0x8, and 0xC" that is listed on some PowerArchitecture chips: https://www.nxp.com/files-static/32bit/doc/errata/MPC8379ECE.pdf Even though eSDHC-A001 is not documented on the i.MX51 errata document, I have confirmed with the NXP design team that this erratum does affect i.MX51, so fix the problem by selecting SYS_FSL_ERRATUM_ESDHC_A001 at SoC level. The i.MX51 ts4800 board already selects this option, but it is better to move this selection to the i.MX51 SoC level instead. Successfully tested with a high speed SD card on a mx51evk board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> |
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| .. | ||
| mx2 | ||
| mx5 | ||
| mx6 | ||
| mx7 | ||
| mx7ulp | ||
| cache.c | ||
| cmd_bmode.c | ||
| cmd_dek.c | ||
| cmd_hdmidet.c | ||
| cpu.c | ||
| ddrmc-vf610.c | ||
| hab.c | ||
| i2c-mxv7.c | ||
| imx_bootaux.c | ||
| init.c | ||
| iomux-v3.c | ||
| Kconfig | ||
| Makefile | ||
| misc.c | ||
| rdc-sema.c | ||
| sata.c | ||
| speed.c | ||
| spl_sd.cfg | ||
| spl.c | ||
| syscounter.c | ||
| timer.c | ||
| video.c | ||