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d8fc1ef2f0
When AE350 boots from flash, use CONFIG_OF_SEPARATE instead of CONFIG_OF_BOARD. Also remove unused code about prior_stage_fdt_address. And modify CONFIG_SYS_FDT_BASE as flash address. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
150 lines
3.7 KiB
C
150 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* CPU and Board Configuration Options
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*/
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#define CONFIG_BOOTP_SEND_HOSTNAME
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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/*
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* Print Buffer Size
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*/
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/*
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* max number of command args
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*/
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#define CONFIG_SYS_MAXARGS 16
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/*
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* Boot Argument Buffer Size
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*/
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/*
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* Size of malloc() pool
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* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
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*/
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#define CONFIG_SYS_MALLOC_LEN (512 << 10)
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/* DT blob (fdt) address */
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#define CONFIG_SYS_FDT_BASE 0x800f0000
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/*
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* Physical Memory Map
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*/
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#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1 \
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(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
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#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
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#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
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/*
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* Serial console configuration
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#ifndef CONFIG_DM_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#endif
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#define CONFIG_SYS_NS16550_CLK 19660800
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/* Init Stack Pointer */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
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GENERATED_GBL_DATA_SIZE)
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/*
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* Load address and memory test area should agree with
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* arch/riscv/config.mk. Be careful not to overwrite U-Boot itself.
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */
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/*
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* memtest works on 512 MB in DRAM
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*/
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
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/*
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* FLASH and environment organization
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*/
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/* use CFI framework */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
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/* support JEDEC */
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#ifdef CONFIG_CFI_FLASH
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#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
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#endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
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#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
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/* max number of memory banks */
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/*
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* There are 4 banks supported for this Controller,
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* but we have only 1 bank connected to flash on board
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*/
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#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#endif
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#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
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/* max number of sectors on one chip */
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#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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/* environments */
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#define CONFIG_ENV_SECT_SIZE 0x1000
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#define CONFIG_ENV_OVERWRITE
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/* SPI FLASH */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 16 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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/* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
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/* Increase max gunzip size */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20)
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/* When we use RAM as ENV */
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#define CONFIG_ENV_SIZE 0x2000
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/* Enable distro boot */
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kernel_addr_r=0x00080000\0" \
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"pxefile_addr_r=0x01f00000\0" \
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"scriptaddr=0x01f00000\0" \
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"fdt_addr_r=0x02000000\0" \
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"ramdisk_addr_r=0x02800000\0" \
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BOOTENV
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#endif /* __CONFIG_H */
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