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https://github.com/u-boot/u-boot.git
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d3f871482f
The environment is the canonical storage location of the mac address, so we're killing off the global data location and moving everything to querying the env directly. The drivers that get converted here: 3c589 4xx_enet dc2114x dm9000x enc28j60 fsl_mcdmafec ks8695eth mcffec rtl8019 rtl8169 s3c4510b_eth xilinx_emac xilinx_emaclite Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Ben Warren <biggerbadderben@gmail.com> CC: Rolf Offermanns <rof@sysgo.de> CC: Stefan Roese <sr@denx.de> CC: Sascha Hauer <saschahauer@web.de> CC: TsiChung Liew <Tsi-Chung.Liew@freescale.com> CC: Greg Ungerer <greg.ungerer@opengear.com> CC: Xue Ligong <lgxue@hotmail.com> CC: Masami Komiya <mkomiya@sonare.it> CC: Curt Brune <curt@cucy.com> CC: Michal SIMEK <monstr@monstr.eu>
242 lines
7.2 KiB
C
242 lines
7.2 KiB
C
/***********************************************************************
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*
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* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
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* Curt Brune <curt@cucy.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Description: Ethernet interface for Samsung S3C4510B SoC
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*/
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#include <common.h>
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#include <command.h>
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#include <net.h>
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#include <asm/hardware.h>
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#include "s3c4510b_eth.h"
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static TX_FrameDescriptor txFDbase[ETH_MaxTxFrames];
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static MACFrame txFrameBase[ETH_MaxTxFrames];
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static RX_FrameDescriptor rxFDbase[PKTBUFSRX];
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static ETH m_eth;
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static s32 TxFDinit( ETH *eth) {
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s32 i;
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MACFrame *txFrmBase;
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/* disable cache for access to the TX buffers */
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txFrmBase = (MACFrame *)( (u32)txFrameBase | CACHE_DISABLE_MASK);
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/* store start of Tx descriptors and set current */
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eth->m_curTX_FD = (TX_FrameDescriptor *) ((u32)txFDbase | CACHE_DISABLE_MASK);
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eth->m_baseTX_FD = eth->m_curTX_FD;
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for ( i = 0; i < ETH_MaxTxFrames; i++) {
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eth->m_baseTX_FD[i].m_frameDataPtr.bf.dataPtr = (u32)&txFrmBase[i];
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eth->m_baseTX_FD[i].m_frameDataPtr.bf.owner = 0x0; /* CPU owner */
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eth->m_baseTX_FD[i].m_opt.ui = 0x0;
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eth->m_baseTX_FD[i].m_status.ui = 0x0;
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eth->m_baseTX_FD[i].m_nextFD = ð->m_baseTX_FD[i+1];
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}
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/* make the list circular */
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eth->m_baseTX_FD[i-1].m_nextFD = ð->m_baseTX_FD[0];
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PUT_REG( REG_BDMATXPTR, (u32)eth->m_curTX_FD);
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return 0;
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}
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static s32 RxFDinit( ETH *eth) {
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s32 i;
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/* MACFrame *rxFrmBase; */
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/* disable cache for access to the RX buffers */
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/* rxFrmBase = (MACFrame *)( (u32)rxFrameBase | CACHE_DISABLE_MASK); */
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/* store start of Rx descriptors and set current */
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eth->m_curRX_FD = (RX_FrameDescriptor *)((u32)rxFDbase | CACHE_DISABLE_MASK);
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eth->m_baseRX_FD = eth->m_curRX_FD;
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for ( i = 0; i < PKTBUFSRX; i++) {
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eth->m_baseRX_FD[i].m_frameDataPtr.bf.dataPtr = (u32)NetRxPackets[i] | CACHE_DISABLE_MASK;
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eth->m_baseRX_FD[i].m_frameDataPtr.bf.owner = 0x1; /* BDMA owner */
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eth->m_baseRX_FD[i].m_reserved = 0x0;
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eth->m_baseRX_FD[i].m_status.ui = 0x0;
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eth->m_baseRX_FD[i].m_nextFD = ð->m_baseRX_FD[i+1];
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}
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/* make the list circular */
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eth->m_baseRX_FD[i-1].m_nextFD = ð->m_baseRX_FD[0];
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PUT_REG( REG_BDMARXPTR, (u32)eth->m_curRX_FD);
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return 0;
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}
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/*
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* Public u-boot interface functions below
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*/
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int eth_init(bd_t *bis)
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{
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ETH *eth = &m_eth;
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/* store our MAC address */
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eth_getenv_enetaddr("ethaddr", eth->m_mac);
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/* setup DBMA and MAC */
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PUT_REG( REG_BDMARXCON, ETH_BRxRS); /* reset BDMA RX machine */
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PUT_REG( REG_BDMATXCON, ETH_BTxRS); /* reset BDMA TX machine */
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PUT_REG( REG_MACCON , ETH_SwReset); /* reset MAC machine */
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PUT_REG( REG_BDMARXLSZ, sizeof(MACFrame));
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PUT_REG( REG_MACCON , 0); /* reset MAC machine */
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/* init frame descriptors */
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TxFDinit( eth);
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RxFDinit( eth);
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/* init the CAM with our MAC address */
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PUT_REG( REG_CAM_BASE, (eth->m_mac[0] << 24) |
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(eth->m_mac[1] << 16) |
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(eth->m_mac[2] << 8) |
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(eth->m_mac[3]));
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PUT_REG( REG_CAM_BASE + 0x4, (eth->m_mac[4] << 24) |
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(eth->m_mac[5] << 16));
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/* enable CAM address 1 -- the MAC we just loaded */
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PUT_REG( REG_CAMEN, 0x1);
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PUT_REG( REG_CAMCON,
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ETH_BroadAcc | /* accept broadcast packetes */
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ETH_CompEn); /* enable compare mode (check against the CAM) */
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/* configure the BDMA Transmitter control */
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PUT_REG( REG_BDMATXCON,
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ETH_BTxBRST | /* BDMA Tx burst size 16 words */
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ETH_BTxMSL110 | /* BDMA Tx wait to fill 6/8 of the BDMA */
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ETH_BTxSTSKO | /* BDMA Tx interrupt(Stop) on non-owner TX FD */
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ETH_BTxEn); /* BDMA Tx Enable */
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/* configure the MAC Transmitter control */
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PUT_REG( REG_MACTXCON,
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ETH_EnComp | /* interrupt when the MAC transmits or discards packet */
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ETH_TxEn); /* MAC transmit enable */
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/* configure the BDMA Receiver control */
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PUT_REG( REG_BDMARXCON,
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ETH_BRxBRST | /* BDMA Rx Burst Size 16 words */
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ETH_BRxSTSKO | /* BDMA Rx interrupt(Stop) on non-owner RX FD */
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ETH_BRxMAINC | /* BDMA Rx Memory Address increment */
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ETH_BRxDIE | /* BDMA Rx Every Received Frame Interrupt Enable */
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ETH_BRxNLIE | /* BDMA Rx NULL List Interrupt Enable */
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ETH_BRxNOIE | /* BDMA Rx Not Owner Interrupt Enable */
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ETH_BRxLittle | /* BDMA Rx Little endian */
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ETH_BRxEn); /* BDMA Rx Enable */
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/* configure the MAC Receiver control */
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PUT_REG( REG_MACRXCON,
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ETH_RxEn); /* MAC ETH_RxEn */
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return 0;
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}
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/* Send a packet */
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s32 eth_send(volatile void *packet, s32 length)
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{
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u32 i;
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ETH *eth = &m_eth;
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if ( eth->m_curTX_FD->m_frameDataPtr.bf.owner) {
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printf("eth_send(): TX Frame. CPU not owner.\n");
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return -1;
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}
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/* copy user data into frame data pointer */
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memcpy((void *)((u32)(eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr)),
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(void *)packet,
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length);
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/* Set TX Frame flags */
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eth->m_curTX_FD->m_opt.bf.widgetAlign = 0;
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eth->m_curTX_FD->m_opt.bf.frameDataDir = 1;
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eth->m_curTX_FD->m_opt.bf.littleEndian = 1;
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eth->m_curTX_FD->m_opt.bf.macTxIrqEnbl = 1;
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eth->m_curTX_FD->m_opt.bf.no_crc = 0;
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eth->m_curTX_FD->m_opt.bf.no_padding = 0;
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/* Set TX Frame length */
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eth->m_curTX_FD->m_status.bf.len = length;
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/* Change ownership to BDMA */
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eth->m_curTX_FD->m_frameDataPtr.bf.owner = 1;
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/* Enable MAC and BDMA Tx control register */
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SET_REG( REG_BDMATXCON, ETH_BTxEn);
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SET_REG( REG_MACTXCON, ETH_TxEn);
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/* poll on TX completion status */
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while ( !eth->m_curTX_FD->m_status.bf.complete) {
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/* sleep */
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for ( i = 0; i < 0x10000; i ++);
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}
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/* Change the Tx frame descriptor for next use */
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eth->m_curTX_FD = eth->m_curTX_FD->m_nextFD;
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return 0;
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}
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/* Check for received packets */
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s32 eth_rx (void)
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{
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s32 nLen = 0;
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ETH *eth = &m_eth;
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/* check if packet ready */
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if ( (GET_REG( REG_BDMASTAT)) & ETH_S_BRxRDF) {
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/* process all waiting packets */
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while ( !eth->m_curRX_FD->m_frameDataPtr.bf.owner) {
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nLen = eth->m_curRX_FD->m_status.bf.len;
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/* call back u-boot -- may call eth_send() */
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NetReceive ((u8 *)eth->m_curRX_FD->m_frameDataPtr.ui, nLen);
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/* set owner back to CPU */
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eth->m_curRX_FD->m_frameDataPtr.bf.owner = 1;
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/* clear status */
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eth->m_curRX_FD->m_status.ui = 0x0;
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/* advance to next descriptor */
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eth->m_curRX_FD = eth->m_curRX_FD->m_nextFD;
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/* clear received frame bit */
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PUT_REG( REG_BDMASTAT, ETH_S_BRxRDF);
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}
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}
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return nLen;
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}
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/* Halt ethernet engine */
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void eth_halt(void)
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{
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/* disable MAC */
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PUT_REG( REG_MACCON, ETH_HaltReg);
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}
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