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9452d58e10
This patch converts the dart6ul ethernet support to DM_ETH and cleans up the legacy ethernet code. The clean up, more specifically: * moves the fec2 node and pin definition to the carrier board DTS since the phy associated with it is on the carrier board and not on the SoM; * add the reset pin associated to each phy; * separate the ethernet, mdio and reset pins of each fec so that they are easier to reference; * add clock properties to the phy nodes since they are connected to the 50Mhz ENET[12]_TX_CLK clock of the SoC; * remove CONFIG_BOARD_EARLY_INIT_F since the function is now empty. Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Board configuration file for Variscite DART-6UL Evaluation Kit
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* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
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*/
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#ifndef __DART_6UL_H
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#define __DART_6UL_H
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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#include "mx6_common.h"
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/* SPL options */
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#include "imx6_spl.h"
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/* NAND pin conflicts with usdhc2 */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_SYS_FSL_USDHC_NUM 1
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#else
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#endif
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#ifdef CONFIG_CMD_NET
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#define CONFIG_FEC_ENET_DEV 0
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#if (CONFIG_FEC_ENET_DEV == 0)
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#define CONFIG_ETHPRIME "eth0"
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#elif (CONFIG_FEC_ENET_DEV == 1)
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#define CONFIG_ETHPRIME "eth1"
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#endif
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#endif
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
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/* Environment settings */
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/* Environment in SD */
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#define MMC_ROOTFS_DEV 0
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#define MMC_ROOTFS_PART 2
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/* Console configs */
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#define CONFIG_MXC_UART_BASE UART1_BASE
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/* MMC Configs */
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#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
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#define CONFIG_SUPPORT_EMMC_BOOT
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/* I2C configs */
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#ifdef CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_SPEED 100000
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#endif
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_HZ 1000
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/* Physical Memory Map */
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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#define PHYS_SDRAM_SIZE SZ_512M
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* USB Configs */
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define ENV_MMC \
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"mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
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"mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
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"fitpart=1\0" \
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"bootdelay=3\0" \
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"silent=1\0" \
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"optargs=rw rootwait\0" \
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"mmcautodetect=yes\0" \
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"mmcrootfstype=ext4\0" \
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"mmcfit_name=fitImage\0" \
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"mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \
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"${mmcfit_name}\0" \
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"mmcargs=setenv bootargs " \
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"root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \
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"console=${console} rootfstype=${mmcrootfstype}\0" \
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"mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \
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/* Default environment */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0xffffffff\0" \
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"console=ttymxc0,115200n8\0" \
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"addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
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"fit_addr=0x82000000\0" \
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ENV_MMC
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#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit"
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(MMC, mmc, 1) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#endif /* __DART_6UL_H */
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