mirror of
https://github.com/u-boot/u-boot.git
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201 lines
4.9 KiB
C
201 lines
4.9 KiB
C
/*
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* (C) Copyright 2000, 2001
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include "du405.h"
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#include <asm/processor.h>
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#include <ppc4xx.h>
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#include <405gp_i2c.h>
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#include <command.h>
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#include <cmd_boot.h>
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/* ------------------------------------------------------------------------- */
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#if 0
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#define FPGA_DEBUG
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#endif
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#if 0
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#define FPGA_DEBUG2
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#endif
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/* fpga configuration data - generated by bin2cc */
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const unsigned char fpgadata[] = {
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#include "fpgadata.c"
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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int board_pre_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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int index, len, i;
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int status;
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#ifdef FPGA_DEBUG
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/* set up serial port with default baudrate */
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(void) get_clocks ();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init ();
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console_init_f ();
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#endif
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/*
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* Boot onboard FPGA
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*/
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status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
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if (status != 0) {
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/* booting FPGA failed */
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#ifndef FPGA_DEBUG
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/* set up serial port with default baudrate */
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(void) get_clocks ();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init ();
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console_init_f ();
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#endif
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printf ("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf ("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf ("FPGA: %s\n", &(fpgadata[index + 1]));
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index += len + 3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i = 20; i > 0; i--) {
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printf ("Rebooting in %2d seconds \r", i);
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for (index = 0; index < 1000; index++)
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udelay (1000);
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}
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putc ('\n');
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do_reset (NULL, 0, 0, NULL);
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}
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive
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* IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive
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* IRQ 28 (EXT IRQ 3) unused; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr (uicer, 0x00000000); /* disable all ints */
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mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
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mtdcr (uicpr, 0xFFFFFFB1); /* set int polarities */
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mtdcr (uictr, 0x10000000); /* set int trigger levels */
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mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 100 us
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*/
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mtebc (epcr, 0xb8400000);
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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int index;
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int len;
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unsigned char str[64];
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int i = getenv_r ("serial#", str, sizeof (str));
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming DU405");
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} else {
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puts (str);
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}
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puts ("\nFPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf ("%s ", &(fpgadata[index + 1]));
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index += len + 3;
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}
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putc ('\n');
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/*
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* Reset external DUART via FPGA
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*/
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*(volatile unsigned char *) FPGA_MODE_REG = 0xff; /* reset high active */
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*(volatile unsigned char *) FPGA_MODE_REG = 0x00; /* low again */
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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return (16 * 1024 * 1024);
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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