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aa6e94deab
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
166 lines
5.2 KiB
C
166 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* Configuation settings for the AT91SAM9263EK board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <linux/stringify.h>
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/*
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* SoC must be defined first, before hardware.h is included.
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* In this case SoC is defined in boards.cfg.
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*/
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#include <asm/hardware.h>
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
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/* SDRAM */
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#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CFG_SYS_SDRAM_SIZE 0x04000000
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#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
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#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
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/* NOR flash, if populated */
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#ifdef CONFIG_SYS_USE_NORFLASH
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#define PHYS_FLASH_1 0x10000000
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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/* Address and size of Primary Environment Sector */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
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"update=" \
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"protect off ${monitor_base} +${filesize};" \
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"erase ${monitor_base} +${filesize};" \
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"cp.b ${fileaddr} ${monitor_base} ${filesize};" \
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"protect on ${monitor_base} +${filesize}\0"
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#define MASTER_PLL_MUL 171
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#define MASTER_PLL_DIV 14
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#define MASTER_PLL_OUT 3
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/* clocks */
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#define CONFIG_SYS_MOR_VAL \
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(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
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#define CONFIG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLAR_29 | \
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AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
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AT91_PMC_PLLXR_PLLCOUNT(63) | \
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AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
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AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR1_VAL \
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(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
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AT91_PMC_MCKR_MDIV_2)
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR2_VAL \
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(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
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AT91_PMC_MCKR_MDIV_2)
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/* define PDC[31:16] as DATA[31:16] */
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#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
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/* no pull-up for D[31:16] */
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#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
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/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
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#define CONFIG_SYS_MATRIX_EBICSA_VAL \
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(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
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AT91_MATRIX_CSA_EBI_CS1A)
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/* SDRAM */
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/* SDRAMC_MR Mode register */
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#define CONFIG_SYS_SDRC_MR_VAL1 0
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/* SDRAMC_TR - Refresh Timer register */
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#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
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/* SDRAMC_CR - Configuration register*/
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#define CONFIG_SYS_SDRC_CR_VAL \
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(AT91_SDRAMC_NC_9 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_3 | \
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AT91_SDRAMC_DBW_32 | \
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(1 << 8) | /* Write Recovery Delay */ \
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(7 << 12) | /* Row Cycle Delay */ \
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(2 << 16) | /* Row Precharge Delay */ \
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(2 << 20) | /* Row to Column Delay */ \
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(5 << 24) | /* Active to Precharge Delay */ \
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(1 << 28)) /* Exit Self Refresh to Active Delay */
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/* Memory Device Register -> SDRAM */
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#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
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#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
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#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
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#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
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#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
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#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
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#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
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/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
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#define CONFIG_SYS_SMC0_SETUP0_VAL \
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(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
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AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
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#define CONFIG_SYS_SMC0_PULSE0_VAL \
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(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
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AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
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#define CONFIG_SYS_SMC0_CYCLE0_VAL \
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(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
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#define CONFIG_SYS_SMC0_MODE0_VAL \
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(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
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AT91_SMC_MODE_DBW_16 | \
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AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
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/* user reset enable */
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#define CONFIG_SYS_RSTC_RMR_VAL \
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(AT91_RSTC_KEY | \
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AT91_RSTC_MR_URSTEN | \
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AT91_RSTC_MR_ERSTL(15))
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/* Disable Watchdog */
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#define CONFIG_SYS_WDTC_WDMR_VAL \
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(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
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AT91_WDT_MR_WDV(0xfff) | \
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AT91_WDT_MR_WDDIS | \
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AT91_WDT_MR_WDD(0xfff))
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#endif
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#include <linux/stringify.h>
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#endif
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
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/* our ALE is AD21 */
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#define CFG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CFG_SYS_NAND_MASK_CLE (1 << 22)
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#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
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#define CFG_SYS_NAND_READY_PIN AT91_PIN_PA22
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#endif
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/* USB */
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
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#endif
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