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b2a6dfe4f8
We do not have to define CONFIG_MPC5xxx in board config headers (and start.S) because it is defined in arch/powerpc/cpu/mpc5xxx/config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
420 lines
12 KiB
C
420 lines
12 KiB
C
/*
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* (C) Copyright 2009
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* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
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*
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* (C) Copyright 2003-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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#define CONFIG_INKA4X0 1 /* INKA4x0 board */
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/*
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* Valid values for CONFIG_SYS_TEXT_BASE are:
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* 0xFFE00000 boot low
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* 0x00100000 boot from RAM (for testing only)
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*/
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */
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#endif
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
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#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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*/
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#define CONFIG_PCI_SCAN_SHOW 1
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#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CONFIG_SYS_XLB_PIPELINING 1
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SNTP
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#define CONFIG_CMD_USB
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#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
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#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */
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# define CONFIG_SYS_LOWBOOT 1
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#endif
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_ETHADDR 00:a0:a4:03:00:00
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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#define CONFIG_IPADDR 192.168.100.2
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#define CONFIG_SERVERIP 192.168.100.1
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#define CONFIG_NETMASK 255.255.255.0
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#define HOSTNAME inka4x0
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#define CONFIG_BOOTFILE "/tftpboot/inka4x0/uImage"
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#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addcons=setenv bootargs ${bootargs} " \
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"console=ttyS0,${baudrate}\0" \
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"flash_nfs=run nfsargs addip addcons;" \
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"bootm ${kernel_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};" \
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"run nfsargs addip addcons;bootm\0" \
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"enable_disp=mw.l 100000 04000000 1;" \
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"cp.l 100000 f0000b20 1;" \
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"cp.l 100000 f0000b28 1\0" \
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"ideargs=setenv bootargs root=/dev/hda1 rw\0" \
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"ide_boot=ext2load ide 0:1 200000 uImage;" \
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"run ideargs addip addcons enable_disp;bootm\0" \
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"brightness=255\0" \
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""
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#define CONFIG_BOOTCOMMAND "run ide_boot"
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/*
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* IPB Bus clocking configuration.
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*/
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#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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/*
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* Flash configuration
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*/
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_BASE 0xffe00000
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#define CONFIG_SYS_FLASH_SIZE 0x00200000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xF0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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/*
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* SDRAM controller configuration
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*/
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#undef CONFIG_SDR_MT48LC16M16A2
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#undef CONFIG_DDR_MT46V16M16
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#undef CONFIG_DDR_MT46V32M16
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#undef CONFIG_DDR_HYB25D512160BF
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#define CONFIG_DDR_K4H511638C
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/* Use ON-Chip SRAM until RAM will be available */
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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/* preserve space for the post_word at end of on-chip SRAM */
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#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
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#ifdef CONFIG_POST
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
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#else
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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#endif
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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# define CONFIG_SYS_RAMBOOT 1
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#endif
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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#define CONFIG_MPC5xxx_FEC_MII100
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/*
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* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
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*/
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/* #define CONFIG_MPC5xxx_FEC_MII10 */
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#define CONFIG_PHY_ADDR 0x00
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#define CONFIG_MII
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/*
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* GPIO configuration
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*
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* use CS1 as gpio_wkup_6 output
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* Bit 0 (mask: 0x80000000): 0
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* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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* 00 -> No Alternatives, I2C1 is used for onboard EEPROM
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* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
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* EEPROM
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* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
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* use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
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* use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
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* use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101
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*/
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444
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/*
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* RTC configuration
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*/
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#define CONFIG_RTC_RTC4543 1 /* use external RTC */
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/*
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* Software (bit-bang) three wire serial configuration
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*
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* Note that we need the ifdefs because otherwise compilation of
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* mkimage.c fails.
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*/
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#define CONFIG_SOFT_TWS 1
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#ifdef TWS_IMPLEMENTATION
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#include <mpc5xxx.h>
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#include <asm/io.h>
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#define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
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#define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
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#define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
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#define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
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static inline void tws_ce(unsigned bit)
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{
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struct mpc5xxx_wu_gpio *wu_gpio =
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(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
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if (bit)
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setbits_8(&wu_gpio->dvo, TWS_CE);
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else
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clrbits_8(&wu_gpio->dvo, TWS_CE);
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}
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static inline void tws_wr(unsigned bit)
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{
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struct mpc5xxx_wu_gpio *wu_gpio =
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(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
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if (bit)
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setbits_8(&wu_gpio->dvo, TWS_WR);
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else
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clrbits_8(&wu_gpio->dvo, TWS_WR);
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}
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static inline void tws_clk(unsigned bit)
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{
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struct mpc5xxx_gpio *gpio =
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(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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if (bit)
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setbits_8(&gpio->sint_dvo, TWS_CLK);
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else
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clrbits_8(&gpio->sint_dvo, TWS_CLK);
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}
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static inline void tws_data(unsigned bit)
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{
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struct mpc5xxx_gpio *gpio =
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(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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if (bit)
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setbits_8(&gpio->sint_dvo, TWS_DATA);
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else
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clrbits_8(&gpio->sint_dvo, TWS_DATA);
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}
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static inline unsigned tws_data_read(void)
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{
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struct mpc5xxx_gpio *gpio =
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(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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return !!(in_8(&gpio->sint_ival) & TWS_DATA);
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}
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static inline void tws_data_config_output(unsigned output)
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{
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struct mpc5xxx_gpio *gpio =
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(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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if (output)
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setbits_8(&gpio->sint_ddr, TWS_DATA);
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else
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clrbits_8(&gpio->sint_ddr, TWS_DATA);
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}
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#endif /* TWS_IMPLEMENTATION */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/* Enable an alternate, more extensive memory test */
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#define CONFIG_SYS_ALT_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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/*
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* Enable loopw command.
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*/
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#define CONFIG_LOOPW
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/*
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* Various low-level settings
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*/
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#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
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#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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/* 32Mbit SRAM @0x30000000 */
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#define CONFIG_SYS_CS1_START 0x30000000
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#define CONFIG_SYS_CS1_SIZE 0x00400000
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#define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
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/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
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#define CONFIG_SYS_CS2_START 0x80000000
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#define CONFIG_SYS_CS2_SIZE 0x0001000
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#define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
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/* GPIO in @0x30400000 */
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#define CONFIG_SYS_CS3_START 0x30400000
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#define CONFIG_SYS_CS3_SIZE 0x00100000
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#define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
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#define CONFIG_SYS_CS_BURST 0x00000000
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#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
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/*-----------------------------------------------------------------------
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* USB stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_CLOCK 0x00015555
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#define CONFIG_USB_CONFIG 0x00001000
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#define CONFIG_USB_STORAGE
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff Supports IDE harddisk
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#define CONFIG_IDE_PREINIT
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */
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#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */
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#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
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#define CONFIG_ATAPI 1
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#define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */
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#endif /* __CONFIG_H */
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