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6b57ff6fd5
Add Freescale QSPI driver support for VF610. Signed-off-by: Alison Wang <Huan.Wang@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com>
128 lines
3.0 KiB
C
128 lines
3.0 KiB
C
/*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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*
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* Register definitions for Freescale QSPI
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _FSL_QSPI_H_
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#define _FSL_QSPI_H_
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struct fsl_qspi_regs {
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u32 mcr;
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u32 rsvd0[1];
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u32 ipcr;
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u32 flshcr;
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u32 buf0cr;
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u32 buf1cr;
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u32 buf2cr;
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u32 buf3cr;
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u32 bfgencr;
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u32 soccr;
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u32 rsvd1[2];
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u32 buf0ind;
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u32 buf1ind;
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u32 buf2ind;
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u32 rsvd2[49];
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u32 sfar;
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u32 rsvd3[1];
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u32 smpr;
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u32 rbsr;
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u32 rbct;
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u32 rsvd4[15];
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u32 tbsr;
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u32 tbdr;
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u32 rsvd5[1];
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u32 sr;
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u32 fr;
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u32 rser;
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u32 spndst;
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u32 sptrclr;
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u32 rsvd6[4];
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u32 sfa1ad;
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u32 sfa2ad;
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u32 sfb1ad;
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u32 sfb2ad;
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u32 rsvd7[28];
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u32 rbdr[32];
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u32 rsvd8[32];
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u32 lutkey;
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u32 lckcr;
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u32 rsvd9[2];
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u32 lut[64];
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};
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#define QSPI_IPCR_SEQID_SHIFT 24
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#define QSPI_IPCR_SEQID_MASK (0xf << QSPI_IPCR_SEQID_SHIFT)
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#define QSPI_MCR_END_CFD_SHIFT 2
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#define QSPI_MCR_END_CFD_MASK (3 << QSPI_MCR_END_CFD_SHIFT)
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#define QSPI_MCR_END_CFD_LE (1 << QSPI_MCR_END_CFD_SHIFT)
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#define QSPI_MCR_DDR_EN_SHIFT 7
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#define QSPI_MCR_DDR_EN_MASK (1 << QSPI_MCR_DDR_EN_SHIFT)
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#define QSPI_MCR_CLR_RXF_SHIFT 10
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#define QSPI_MCR_CLR_RXF_MASK (1 << QSPI_MCR_CLR_RXF_SHIFT)
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#define QSPI_MCR_CLR_TXF_SHIFT 11
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#define QSPI_MCR_CLR_TXF_MASK (1 << QSPI_MCR_CLR_TXF_SHIFT)
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#define QSPI_MCR_MDIS_SHIFT 14
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#define QSPI_MCR_MDIS_MASK (1 << QSPI_MCR_MDIS_SHIFT)
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#define QSPI_MCR_RESERVED_SHIFT 16
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#define QSPI_MCR_RESERVED_MASK (0xf << QSPI_MCR_RESERVED_SHIFT)
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#define QSPI_SMPR_HSENA_SHIFT 0
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#define QSPI_SMPR_HSENA_MASK (1 << QSPI_SMPR_HSENA_SHIFT)
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#define QSPI_SMPR_FSPHS_SHIFT 5
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#define QSPI_SMPR_FSPHS_MASK (1 << QSPI_SMPR_FSPHS_SHIFT)
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#define QSPI_SMPR_FSDLY_SHIFT 6
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#define QSPI_SMPR_FSDLY_MASK (1 << QSPI_SMPR_FSDLY_SHIFT)
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#define QSPI_SMPR_DDRSMP_SHIFT 16
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#define QSPI_SMPR_DDRSMP_MASK (7 << QSPI_SMPR_DDRSMP_SHIFT)
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#define QSPI_BFGENCR_SEQID_SHIFT 12
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#define QSPI_BFGENCR_SEQID_MASK (0xf << QSPI_BFGENCR_SEQID_SHIFT)
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#define QSPI_BFGENCR_PAR_EN_SHIFT 16
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#define QSPI_BFGENCR_PAR_EN_MASK (1 << QSPI_BFGENCR_PAR_EN_SHIFT)
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#define QSPI_RBSR_RDBFL_SHIFT 8
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#define QSPI_RBSR_RDBFL_MASK (0x3f << QSPI_RBSR_RDBFL_SHIFT)
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#define QSPI_RBCT_RXBRD_SHIFT 8
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#define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT)
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#define QSPI_SR_BUSY_SHIFT 0
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#define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT)
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#define QSPI_LCKCR_LOCK 0x1
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#define QSPI_LCKCR_UNLOCK 0x2
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#define LUT_KEY_VALUE 0x5af05af0
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#define OPRND0_SHIFT 0
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#define OPRND0(x) ((x) << OPRND0_SHIFT)
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#define PAD0_SHIFT 8
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#define PAD0(x) ((x) << PAD0_SHIFT)
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#define INSTR0_SHIFT 10
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#define INSTR0(x) ((x) << INSTR0_SHIFT)
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#define OPRND1_SHIFT 16
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#define OPRND1(x) ((x) << OPRND1_SHIFT)
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#define PAD1_SHIFT 24
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#define PAD1(x) ((x) << PAD1_SHIFT)
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#define INSTR1_SHIFT 26
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#define INSTR1(x) ((x) << INSTR1_SHIFT)
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#define LUT_CMD 1
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#define LUT_ADDR 2
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#define LUT_DUMMY 3
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#define LUT_READ 7
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#define LUT_WRITE 8
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#define LUT_PAD1 0
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#define LUT_PAD2 1
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#define LUT_PAD4 2
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#define ADDR24BIT 0x18
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#define ADDR32BIT 0x20
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#endif /* _FSL_QSPI_H_ */
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