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e4d741f8ab
This converts the following to Kconfig: CONFIG_SYS_MONITOR_BASE Note that for how this is re-used on some PowePC platforms, we introduce CONFIG_SPL_SYS_MONITOR_BASE and CONFIG_TPL_SYS_MONITOR_BASE and use the CONFIG_VAL macro to get the correct value at build time, in the code. Signed-off-by: Tom Rini <trini@konsulko.com>
114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Samsung Electronics
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*
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* Configuration settings for the SAMSUNG EXYNOS5 board.
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*/
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#ifndef __CONFIG_EXYNOS5_COMMON_H
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#define __CONFIG_EXYNOS5_COMMON_H
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#define CONFIG_EXYNOS5 /* Exynos5 Family */
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#include "exynos-common.h"
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#define CONFIG_EXYNOS_SPL
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/* Enable ACE acceleration for SHA1 and SHA256 */
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#define CONFIG_EXYNOS_ACE_SHA
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/* Power Down Modes */
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#define S5P_CHECK_SLEEP 0x00000BAD
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#define S5P_CHECK_DIDLE 0xBAD00000
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#define S5P_CHECK_LPA 0xABAD0000
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/* Offset for inform registers */
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#define INFORM0_OFFSET 0x800
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#define INFORM1_OFFSET 0x804
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#define INFORM2_OFFSET 0x808
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#define INFORM3_OFFSET 0x80c
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/* select serial console configuration */
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#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
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/* Thermal Management Unit */
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#define CONFIG_EXYNOS_TMU
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/* MMC SPL */
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#define COPY_BL2_FNPTR_ADDR 0x02020030
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#define CONFIG_RD_LVL
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
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#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
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#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
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/* SPI */
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/* Ethernet Controllor Driver */
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#ifdef CONFIG_CMD_NET
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#define CONFIG_ENV_SROM_BANK 1
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#endif /*CONFIG_CMD_NET*/
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/* Enable Time Command */
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/* USB */
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/* USB boot mode */
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#define CONFIG_USB_BOOTING
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#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
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#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
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#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 2) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 0) \
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func(PXE, pxe, na) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#ifndef MEM_LAYOUT_ENV_SETTINGS
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/* 2GB RAM, bootm size of 256M, load scripts after that */
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"kernel_addr_r=0x42000000\0" \
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"fdt_addr_r=0x43000000\0" \
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"ramdisk_addr_r=0x43300000\0" \
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"scriptaddr=0x50000000\0" \
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"pxefile_addr_r=0x51000000\0"
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#endif
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#ifndef EXYNOS_DEVICE_SETTINGS
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#define EXYNOS_DEVICE_SETTINGS \
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"stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0"
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#endif
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#ifndef EXYNOS_FDTFILE_SETTING
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#define EXYNOS_FDTFILE_SETTING
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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EXYNOS_DEVICE_SETTINGS \
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EXYNOS_FDTFILE_SETTING \
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MEM_LAYOUT_ENV_SETTINGS \
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BOOTENV
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#endif /* __CONFIG_EXYNOS5_COMMON_H */
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