u-boot/arch/riscv
Rick Chen a1f24875c3 riscv: Add a SYSCON driver for Andestech's PLMT
The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
..
cpu riscv: hang if relocation of secondary harts fails 2019-04-08 09:44:26 +08:00
dts riscv: Remove ae350.dts 2018-12-18 09:56:27 +08:00
include/asm riscv: Add a SYSCON driver for Andestech's PLMT 2019-04-08 09:45:08 +08:00
lib riscv: Add a SYSCON driver for Andestech's PLMT 2019-04-08 09:45:08 +08:00
config.mk riscv: qemu: define standalone load address 2019-01-15 09:36:31 +08:00
Kconfig riscv: Add a SYSCON driver for Andestech's PLMT 2019-04-08 09:45:08 +08:00
Makefile riscv: add Kconfig entries for the code model 2018-12-18 09:56:26 +08:00