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a00dfa042d
u-boot/drivers/clk/rockchip
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Philipp Tomsich a00dfa042d rockchip: clk: rk3368: implement DPLL (DRAM PLL) support 
To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).

This commit implements setting the DPLL (CLK_DDR) and provides PLL
configuration details for the common DRAM operating speeds found on
RK3368 boards.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:32 +02:00
..
clk_rk322x.c rockchip: rk322x: add clock driver 2017-07-11 12:13:45 +02:00
clk_rk3036.c rockchip: clk: rk3036: correct setting for pll integer mode 2017-06-23 16:40:23 +02:00
clk_rk3188.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_rk3288.c rockchip: Init clocks again when chain-loading 2017-06-09 13:45:33 -06:00
clk_rk3328.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_rk3368.c rockchip: clk: rk3368: implement DPLL (DRAM PLL) support 2017-08-13 17:12:32 +02:00
clk_rk3399.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_rv1108.c clk_rv1108.c: Fix unused variable warning 2017-06-23 10:38:05 -04:00
Makefile rockchip: rk322x: add clock driver 2017-07-11 12:13:45 +02:00