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To implement a TPL stage (incl. its DRAM controller setup) for the RK3368, we'll want to configure the DPLL (DRAM PLL). This commit implements setting the DPLL (CLK_DDR) and provides PLL configuration details for the common DRAM operating speeds found on RK3368 boards. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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aspeed | ||
at91 | ||
exynos | ||
renesas | ||
rockchip | ||
tegra | ||
uniphier | ||
clk_bcm6345.c | ||
clk_boston.c | ||
clk_fixed_rate.c | ||
clk_pic32.c | ||
clk_sandbox_test.c | ||
clk_sandbox.c | ||
clk_stm32f7.c | ||
clk_zynq.c | ||
clk_zynqmp.c | ||
clk-uclass.c | ||
Kconfig | ||
Makefile |