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19096aba4f
Enable the SPI flash Bank/Extended address register support for all ZynqMP boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
61 lines
1.4 KiB
Plaintext
61 lines
1.4 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_ZYNQMP=y
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CONFIG_SYS_TEXT_BASE=0x8000000
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CONFIG_SYS_MALLOC_F_LEN=0x8000
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CONFIG_SPL=y
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CONFIG_DEBUG_UART_BASE=0xff000000
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CONFIG_DEBUG_UART_CLOCK=100000000
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# CONFIG_SPL_FS_FAT is not set
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# CONFIG_SPL_LIBDISK_SUPPORT is not set
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CONFIG_DEBUG_UART=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_LOAD_FIT=y
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_SPL_OS_BOOT=y
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CONFIG_SPL_RAM_SUPPORT=y
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CONFIG_SPL_RAM_DEVICE=y
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CONFIG_SPL_ATF=y
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_CLK=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_FPGA_LOADBP=y
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CONFIG_CMD_FPGA_LOADP=y
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CONFIG_CMD_FPGA_LOAD_SECURE=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF=y
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# CONFIG_CMD_NET is not set
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CONFIG_CMD_TIME=y
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CONFIG_CMD_TIMER=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revB"
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM=y
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CONFIG_CLK_ZYNQMP=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQMPPL=y
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CONFIG_MISC=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ZYNQ=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_ISSI=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHY_MARVELL=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_PHY_XILINX_GMII2RGMII=y
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CONFIG_MII=y
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CONFIG_ZYNQ_GEM=y
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CONFIG_DEBUG_UART_ZYNQ=y
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_ZYNQ_SERIAL=y
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CONFIG_SPI=y
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CONFIG_ZYNQMP_GQSPI=y
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CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
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