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https://github.com/u-boot/u-boot.git
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b3f44c21ea
Remove MK_STR from places that consume CONFIG_BOOTFILE to force all definitions to be string literals. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
334 lines
9.8 KiB
C
334 lines
9.8 KiB
C
/*
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* am3517_crane.h - Default configuration for AM3517 CraneBoard.
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*
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* Author: Srinath.R <srinath@mistralsolutions.com>
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*
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* Based on include/configs/am3517evm.h
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*
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* Copyright (C) 2011 Mistral Solutions pvt Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP34XX 1 /* which is a 34XX */
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#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
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#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap3.h>
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/*
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* Display CPU and Board information
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*/
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#define CONFIG_DISPLAY_CPUINFO 1
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#define CONFIG_DISPLAY_BOARDINFO 1
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
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/* initial data */
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/*
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* DDR related
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*/
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#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */
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#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
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/*
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* Hardware drivers
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*/
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 3
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#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
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#define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define CONFIG_GENERIC_MMC 1
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#define CONFIG_MMC 1
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#define CONFIG_OMAP_HSMMC 1
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#define CONFIG_DOS_PARTITION 1
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/*
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* USB configuration
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* Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
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* Enable CONFIG_MUSB_UDC for Device functionalities.
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*/
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#define CONFIG_USB_AM35X 1
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#define CONFIG_MUSB_HCD 1
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#ifdef CONFIG_USB_AM35X
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#ifdef CONFIG_MUSB_HCD
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#define CONFIG_CMD_USB
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#define CONFIG_USB_STORAGE
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#define CONGIG_CMD_STORAGE
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#define CONFIG_CMD_FAT
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#ifdef CONFIG_USB_KEYBOARD
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#define CONFIG_SYS_USB_EVENT_POLL
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#define CONFIG_PREBOOT "usb start"
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#endif /* CONFIG_USB_KEYBOARD */
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#endif /* CONFIG_MUSB_HCD */
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#ifdef CONFIG_MUSB_UDC
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/* USB device configuration */
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#define CONFIG_USB_DEVICE 1
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#define CONFIG_USB_TTY 1
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
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/* Change these to suit your needs */
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#define CONFIG_USBD_VENDORID 0x0451
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#define CONFIG_USBD_PRODUCTID 0x5678
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#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
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#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
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#endif /* CONFIG_MUSB_UDC */
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#endif /* CONFIG_USB_AM35X */
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/* commands to include */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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#define CONFIG_CMD_FAT /* FAT support */
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#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
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#define CONFIG_CMD_I2C /* I2C serial bus support */
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#define CONFIG_CMD_MMC /* MMC support */
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#define CONFIG_CMD_NAND /* NAND support */
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_PING
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#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
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#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
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#undef CONFIG_CMD_IMI /* iminfo */
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#undef CONFIG_CMD_IMLS /* List all found images */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 1
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#define CONFIG_SYS_I2C_BUS 0
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#define CONFIG_SYS_I2C_BUS_SELECT 1
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#define CONFIG_DRIVER_OMAP34XX_I2C 1
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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/*
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* Board NAND Info.
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*/
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access */
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/* nand at CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
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/* NAND devices */
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#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
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#define CONFIG_JFFS2_NAND
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/* nand device jffs2 lives on */
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#define CONFIG_JFFS2_DEV "nand0"
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/* start of jffs2 partition */
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#define CONFIG_JFFS2_PART_OFFSET 0x680000
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#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
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/* Environment information */
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#define CONFIG_BOOTDELAY 10
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x82000000\0" \
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"console=ttyS2,115200n8\0" \
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"mmcdev=0\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"root=/dev/mmcblk0p2 rw " \
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"rootfstype=ext3 rootwait\0" \
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"nandargs=setenv bootargs console=${console} " \
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"root=/dev/mtdblock4 rw " \
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"rootfstype=jffs2\0" \
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"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source ${loadaddr}\0" \
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"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"nandboot=echo Booting from nand ...; " \
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"run nandargs; " \
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"nand read ${loadaddr} 280000 400000; " \
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"bootm ${loadaddr}\0" \
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#define CONFIG_BOOTCOMMAND \
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"if mmc rescan ${mmcdev}; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run nandboot; " \
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"fi; " \
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"fi; " \
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"else run nandboot; fi"
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#define CONFIG_AUTO_COMPLETE 1
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/*
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* Miscellaneous configurable options
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*/
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#define V_PROMPT "AM3517_CRANE # "
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_PROMPT V_PROMPT
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 32 /* max number of command */
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/* args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
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0x01F00000) /* 31MB */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
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/* address */
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/*
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* AM3517 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_HZ 1000
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
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#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/* SDRAM Bank Allocation method */
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#define SDRC_R_B_C 1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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/* Configure the PISMO */
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M
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#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
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#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
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/* on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
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#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_NAND_OMAP_GPMC
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_ENV_IS_IN_NAND 1
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#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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*/
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
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/* Flash banks JFFS2 should use */
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#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
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CONFIG_SYS_MAX_NAND_DEVICE)
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#define CONFIG_SYS_JFFS2_MEM_NAND
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/* use flash_info[2] */
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#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#endif /* __CONFIG_H */
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